Cortex-R4 and Cortex-R4F
Copyright 2009 ARM Limited. All rights reserved
Cortex-R4 and Cortex-R4F
Technical Reference Manual
Chapter Introduction
Cortex-R4 and Cortex-R4F Technical Reference Manual
Chapter Processor Initialization, Resets, and Clocking
Chapter AC Characteristics
Appendix B ECC Schemes
List of Tables
Adfsr and Aifsr bit functions
Dirty register format, with ECC
11-12
Example interlocks 14-11
Table A-18 FPU signals Table C-1
List of Figures
Cache operations C7 format for Set and Way
Vector Catch Register format 11-20
Feedback on
Preface
Identifies the major revision of the product
Using this book
About this book
Product revision status
Typographical
Conventions
Signals
Timing diagrams
Other publications
Further reading
This section lists publications by ARM and by third parties
ARM publications
Feedback on this book
Feedback
ARM welcomes feedback on this product and its documentation
Feedback on this product
Introduction
About the processor
About the architecture
System control coprocessor on Interrupt handling on
Components of the processor
This section describes the main components of the processor
Debug on
Prefetch unit
Data Processing Unit
Floating Point Unit
Load/store unit
TCM interfaces
Instruction and data caches
Memory Protection Unit
AXI slave interface
Error correction and detection
5 L2 AXI interfaces
AXI master interface
Real-time debug facilities
Debug
System performance monitoring
ETM interface
Low interrupt latency
System control coprocessor
Interrupt handling
VIC port
Changes
Return from exception using data from the stack
APB Debug interface
Processor has the following interfaces for external access
External interfaces of the processor
APB Debug interface ETM interface Test interface
Shutdown mode
Power management
Run mode
Standby mode
Atcm
Configurable options
Configurable options
MPU
Btcm
VFP
FPU includeda
B1TCMPCEN
Configurable options at reset Feature Options Register
Atcmpcen
B0TCMPCEN
Atcmrmw
Atcmecen
B0TCMECEN
B1TCMECEN
Instruction decode
Execution pipeline stages
Names of the pipeline stages and their functions are
Write-back of data from the execution pipelines
First stage of data memory access
Iss
Execute stages
Redundant core comparison
Test features
Design flow
Product documentation, design flow, and architecture
Documentation
Architectural information
Build configuration
Configuration inputs
Software configuration
Advanced Microcontroller Bus Architecture protocol
Processor identification
Product revision information
Revision field, Debug ID Register
Variant field, Main ID Register
Revision field, Main ID Register
Variant field, Debug ID Register
Exceptions on
Programmer’s Model
Registers on
Program status registers on
About the programmer’s model
Thumb state
Switching state
Instruction set states
ARM state
Operating modes
Data types
Little-endian format
Memory formats
Byte-invariantbig-endian format Little-endian format
Byte-invariant big-endian format
Register set
Registers
Register mode identifiers Mode Mode identifier
General registers and program counter
N, Z, C, and V bits
Program status registers
IT bits
Q bit
GE bits
J bit
DNM bits
Non-maskable fast interrupts on
E bit
A bit
I and F bits
Modification of PSR bits by MSR instructions
PSR mode bit values
M40 Mode Visible state registers Thumb
M bits
ARM DDI 0363E
Exception entry and exit summary
Reset on Interrupts on Aborts on
Exceptions
Exception entry and exit summary
Leaving an exception
Taking an exception
Interrupt request
Reset
Interrupts
Non-maskable fast interrupts
Fast interrupt request
Program status registers on Non-maskable fast interrupts
Interrupt controller
Interrupt entry flowchart
Interrupt entry sequence
Precise aborts
Aborts
Prefetch aborts
Data aborts
Aborts in Strongly Ordered and Device memory
Imprecise aborts
Supervisor call instruction
Abort handler
Breakpoint instruction
Undefined instruction
Exception vectors
Acceleration of execution environments
Architecture Reference Manual
Unaligned and mixed-endian data access support
Big-endian instruction support
Initialization on
Processor Initialization, Resets, and Clocking
Resets on
Reset modes on
2 CRS
Initialization
Caches on TCM on
1 MPU
Preloading TCMs
Caches
5 TCM
Preloading TCMs with parity or ECC
DMA into TCM
Write to TCM directly from debugger
Using TCMs from reset
NSYSPORESET
Resets
NRESET
PRESETDBGn
Power-on reset
Reset modes
Halt operation
Processor reset
Normal operation
Clock gating
Clocking
AXI interface clocking Clock gating
AXI interface clocking
System Control Coprocessor
System control coprocessor functional groups
About the system control coprocessor
Fcse PID
System control coprocessor register functions
Function Register/operation Reference to description
System performance Performance monitoring
System control and configuration
Configuration Region
TCM control TCM Status
Cache control and configuration
MPU control and configuration
System performance monitor
TCM control and configuration
System performance monitor registers
System validation
ARM DDI 0363E
RAZ
System control coprocessor registers
Register allocation
Number
Enable Undefined MPU Region Access Read/write
Undefined MPU Region Size Read/write
Control Undefined MPU Memory Region Read/write
ARM DDI 0363E
Count Undefined
Undefined C3-c11 C12 Performance Monitor Read/write
Event Select Read/write Unpredictable Performance Monitor
Writes Context ID Read/write
C14 User Enable Read/write
Undefined C1-c15 C12 C0-c15 C13
RAZ,ignore
7shows the arrangement of bits in the register
2 c0, Main ID Register
Bits Field Function
3 c0, Cache Type Register
Main ID Register bit functions
TCM Type Register bit functions Bits Field Function
To access the Cache Type Register, read CP15 with
4 c0, TCM Type Register
Cache Type Register bit functions Bits Field Function
TCM Type Register bit functions
To access the TCM Type Register, read CP15 with
To access the MPU Type Register, read CP15 with
5 c0, MPU Type Register
6 c0, Multiprocessor ID Register
Processor Feature Registers
C0, Processor Feature Register 0, PFR0
Processor Feature Register 1 bit functions
To access the Processor Feature Register 0 read CP15 with
C0, Processor Feature Register 1, PFR1
Processor Feature Register 0 bit functions
3124 Reserved
To access the Processor Feature Register 1 read CP15 with
8 c0, Debug Feature Register
Debug Feature Register 0 bit functions
C0, Memory Model Feature Register 0, MMFR0
To access the Debug Feature Register 0 read CP15 with
9 c0, Auxiliary Feature Register
Memory Model Feature Registers
10 Memory Model Feature Register 0 bit functions
C0, Memory Model Feature Register 1, MMFR1
11 Memory Model Feature Register 1 bit functions
16 Memory Model Feature Register 1 format
DMB
C0, Memory Model Feature Register 2, MMFR2
WFI
3112 Reserved
C0, Memory Model Feature Register 3, MMFR3
13 Memory Model Feature Register 3 bit functions
14 Instruction Set Attributes Register 0 bit functions
Instruction Set Attributes Registers
C0, Instruction Set Attributes Register 0, ISAR0
20 Instruction Set Attributes Register 1 format
C0, Instruction Set Attributes Register 1, ISAR1
Indicates support for if then instructions
C0, Instruction Set Attributes Register 2, ISAR2
ITE
Indicates support for PSR instructions
16 Instruction Set Attributes Register 2 bit functions
PSR
Thumb instruction sets
C0, Instruction Set Attributes Register 3, ISAR3
17 Instruction Set Attributes Register 3 bit functions
23 Instruction Set Attributes Register 4 format
C0, Instruction Set Attributes Register 4, ISAR4
18 Instruction Set Attributes Register 4 bit functions
C0, Instruction Set Attributes Registers
12 c0, Current Cache Size Identification Register
8KB
4KB
3130 Reserved
13 c0, Current Cache Level ID Register
15 c1, System Control Register
14 c0, Cache Size Selection Register
Nmfi
23 System Control Register bit functions
AFE
TRE
= strict alignment fault checking enabled
Enables L1 data cache
= data caching disabled. This is the reset value
= data caching enabled
24 Auxiliary Control Register bit functions
Auxiliary Control Registers
C1, Auxiliary Control Register
Deolp
Axiscen
Axiscuen
Dilsm
Dnch
Rsdis
Dbwr
Dlfo
C15, Secondary Auxiliary Control Register
25 Secondary Auxiliary Control Register bit functions
UFC
Doofmacs
IXC
OFC
Atcmecc
17 c1, Coprocessor Access Register
Primary input RMWENRAM1 defines the reset value
Primary input RMWENRAM0 defines the reset value
All other encodings for these FSR bits are Reserved
Fault Status and Address Registers
C5, Data Fault Status Register
To use the Dfsr read or write CP15 with
C5, Instruction Fault Status Register
28 Data Fault Status Register bit functions
29 Instruction Fault Status Register bit functions
To access the Ifsr read or write CP15 with
C5, Auxiliary Fault Status Registers
There are two auxiliary fault status registers
= Btcm
C6, Data Fault Address Register
30 Adfsr and Aifsr bit functions
= Atcm
19 c6, MPU memory region programming registers
C6, Instruction Fault Address Register
C6, MPU Region Base Address Registers
C6, MPU Region Size and Enable Registers
32 Region Size Register bit functions
C6, MPU Region Access Control Registers
158 Sub-region disable
TEX
33 MPU Region Access Control Register bit functions
35 MPU Memory Region Number Register bit functions
34 Access data permission bit encoding
C6, MPU Memory Region Number Register
UNP
Point of Unification PoU
Cache operations
Point of Coherency PoC
Set and Way format
Invalidate and clean operations
37 Widths of the set field for L1 cache sizes Size Set
37shows the cache sizes and the resultant bit range for Set
Address format
36 Functional bits of c7 for Set and Way
38 Functional bits of c7 for address format Bits Field
Data Synchronization Barrier operation
Data Memory Barrier operation
21 c9, Btcm Region Register
39 Btcm Region Register bit functions
To access the Btcm Region Register, read or write CP15 with
22 c9, Atcm Region Register
40 Atcm Region Register bit functions
To access the Atcm Region Register, read or write CP15 with
23 c9, TCM Selection Register
24 c11, Slave Port Control Register
RAZ/UNP
25 c13, Fcse PID Register
26 c13, Context ID Register
312 Reserved
27 c13, Thread and Process ID Registers
Ccnt overflow IRQ request
C15, nVAL IRQ Enable Set Register
Validation Registers
Ccnt overflow FIQ request
C15, nVAL FIQ Enable Set Register
Ccnt overflow reset request
C15, nVAL Reset Enable Set Register
C15, nVAL Debug Request Enable Set Register
Ccnt overflow debug request
C15, nVAL IRQ Enable Clear Register
48 nVAL IRQ Enable Clear Register format
C15, nVAL FIQ Enable Clear Register
303 Reserved UNP or Sbzp
C15, nVAL Reset Enable Clear Register
51 nVAL Debug Request Enable Clear Register format
C15, nVAL Debug Request Enable Clear Register
B0000 4kB B0001 8kB B0011 16kB B0111 32kB B1111 64kB
C15, nVAL Cache Size Override Register
50 nVAL Cache Size Override Register
318 Reserved
53 Correctable Fault Location Register cache
Correctable Fault Location Register
52 Correctable Fault Location Register cache
C15, Build Options 2 Register
To access the Build Options 1 Register, write CP15 with
Build Options Registers
C15, Build Options 1 Register
Atcmes
55 Build Options 2 Register
Noicache
Nodcache
Nompu
Btcmes
Noie
Nofpu
Axibusparity
To access the Build Options 2 Register, write CP15 with
Noharderrorcach
Dcachees
Prefetch Unit
About the prefetch unit
Disabling program flow prediction
Branch prediction
Incorrect predictions and correction
Configuring the branch predictor
Branch predictor
Return stack
Events and Performance Monitor
Event
Bit position Update Value
About the events
Event bus interface bit functions
ETMEXTOUT1
ETMEXTOUT0
Dual issue case B1, B2, F2 load/store, F2D
Non-cacheable access on AXI master bus
Instruction cache access
But with different attributes Dual issue case a branch
TCM correctable ECC error reported by prefetch unit Yes
TCM correctable ECC error reported by load/store unit Yes
About the PMU
2shows how the bit values correspond with the Pmnc Register
Performance monitoring registers
Performance monitoring registers are described
1 c9, Performance Monitor Control Register
Pmnc Register bit functions
2 c9, Count Enable Set Register
Cntens Register bit functions Bits Field Function
To access the Cntens Register, read or write CP15 with
3 c9, Count Enable Clear Register
Cntenc Register bit functions Bits Field Function
To access the Cntenc Register, read or write CP15 with
Cycle counter enable clear
4 c9, Overflow Flag Status Register
5 c9, Software Increment Register
To access the Flag Register, read or write CP15 with
5shows how the bit values correspond with the Flag Register
313 Reserved RAZ on reads, Sbzp on writes Increment Counter
To access the Swincr Register, read or write CP15 with
6 c9, Performance Counter Selection Register
Swincr Register bit functions Bits Field Function
SEL
7 c9, Cycle Count Register
8 c9, Event Selection Register
EVTSELx Register bit functions
To access the EVTSELx Register, read or write CP15 with
Useren Register bit functions
10 c9, User Enable Register
9 c9, Performance Monitor Count Registers
10 Intens Register bit functions Bits Field Function
11 c9, Interrupt Enable Set Register
Ccnt overflow interrupt enable
11 Intenc Register bit functions Bits Field Function
12 c9, Interrupt Enable Clear Register
Ccnt overflow interrupt enable bit
To access the Intenc Register, read or write CP15 with
Use of the event bus and counters
Event bus interface
Memory Protection Unit
MPU faults on
MPU software-accessible registers on
True
Default memory map
About the MPU
Subregions
Memory regions
Region base address
Region size
Region
Region access permissions
Region attributes
Overlapping regions
Example of using subregions
Example of using regions that overlap
TCM regions
Background regions
Memory types
Using memory types
ARM DDI 0363E
TEX20, C, and B encodings Description Memory Type Shareable?
Region attributes
1BB
Cacheable memory policies
Following code is an example of disabling the MPU
On page 7-2shows the default memory map
MPU interaction with memory system
Permission fault
MPU faults
Background fault Permission fault Alignment fault
Background fault
On page 4-5shows the CP15 registers that control the MPU
MPU software-accessible registers
Level One Memory System
About the L1 memory system
L1 memory system block diagram
Parity
About the error detection and correction schemes
Parity Bit ECC on
Read-Modify-Write
Error checking and correction
Hard errors
Bit ECC
Correct-and-retry
Error correction
Correct inline
MPU faults
Fault handling
Faults
Classes of fault that can occur are
TCM external faults
External faults
Cache and TCM parity and ECC errors
Abort exceptions
Fault status information
Debug events
Precise and imprecise aborts
Usage models
Precise abort exceptions
Imprecise abort exceptions
AXI
Correctable errors
Types of aborts Conditions Source Precise Fatal
ARM DDI 0363E
TCM attributes and permissions
About the TCMs
Handling TCM parity errors on Handling TCM ECC errors on
Atcm and Btcm configuration
TCM internal error detection and correction
TCM arbitration
Handling TCM parity errors
Handling TCM ECC errors
TCM port protocol
External TCM errors
TCM initialization
AXI slave interfaces for TCMs
Store buffer
About the caches
Store buffer draining
Cache maintenance operations
Store buffer merging
Store buffer behavior
Error build options
Cache error detection and correction
Cache parity error behavior Value Behavior
Address decoder faults
Handling cache parity errors
Cache ECC error behavior Value Behavior
Handling cache ECC errors
Errors on evictions
Errors on instruction cache read
Errors on data cache read
Errors on data cache write
Invalidate all instruction cache
Clean data cache by set/way
Tag RAM
Cache RAM organization
Tag RAM
Dirty RAM on Data RAM on
Organization of a dirty RAM line
Dirty RAM
Data RAM
Cache sizes and tag RAM organization Tag RAM organization
Nonsequential read operation performed with one RAM access
Data RAM sizes without parity or ECC implemented
13 Data cache RAM bits, with parity Description
15 Data cache data RAM sizes with ECC Cache size Data RAMs
Cache interaction with memory system
Disabling or enabling all of the caches
Following code is an example of enabling caches
Disabling or enabling data cache
Disabling or enabling error checking
Disabling or enabling instruction cache
MCR p15 R0, c1 Write System Control Register
Internal exclusive monitor
Memory types and L1 memory system behavior
Data-cache error events
Error detection events
TCM error events
Instruction-cache error events
ARM DDI 0363E
Level Two Interface
About the L2 interface
Attribute Value Comments
AXI master interface
1shows the AXI master interface attributes
Write response
Identifiers for AXI bus accesses
Outstanding write/read access on different IDs
Outstanding write accesses with the same ID
Aruserm and Awuserm encodings
Eviction buffer
Memory attributes
Arcachem and Awcachem encodings Encoding a Meaning
Memory system implications for AXI accesses
Linefills on
AXI master interface transfers
Strongly Ordered and Device transactions on
Address20
Restrictions on AXI transfers
Strongly Ordered and Device transactions
Non-cacheable Ldrb
Ldrh from Strongly Ordered or Device memory Address30
LDR or LDM that transfers one register
LDM5, Strongly Ordered or Device memory Address40
LDM that transfers five registers
Strh to Strongly Ordered or Device memory Address20
Strb to Strongly Ordered or Device memory Address40
First Wstrbm
STR or STM of one register
STM of seven registers
Non-cacheable reads
Linefills
Cache line write-back eviction
15 LDR or LDM1 from Non-cacheable Normal memory Address20
14 Ldrh from Non-cacheable Normal memory Address20
Non-cacheable or write-through writes
AXI transaction splitting
20 AXI transaction splitting, data in two cache lines
Normal write merging
Example 9-1 Write merging
ARM DDI 0363E
AXI slave interface for cache RAMs
AXI slave interface
AXI slave control
TCM parity and ECC support
Cache parity and ECC support
25 AXI slave interface attributes
AXI slave characteristics
Enabling or disabling AXI slave accesses
26 RAM region decode AxUSERS bit One-hot RAM select
Accessing RAMs using the AXI slave interface
TCM RAM access on Cache RAM access on
RAM selected
TCM RAM access
ARADDRSMSB, see Table
27 TCM chip-select decode Btcm ports
This section contains the following
Cache RAM access
Memory map when accessing the cache RAMs
0001 Bank 0010 0100 1000
Data RAM access
0010 Bank 0100 1000
31 Cache data RAM bank/address decode Inputs ARADDRS1815
35 Data format, data cache, with ECC Data bit Description
34 Data format, instruction cache, with ECC
Tag RAM access
ARM DDI 0363E
43 Dirty register format, with ECC Data bit Description
Dirty RAM access
ARADDRS1815 = 4b1111
Other examples of accessing cache RAMs
About power control on Power management on
Power Control
About power control
Shutdown mode
Run mode
Standby mode
Dormant mode
Communication to the Power Management Controller
Debug state on Cache debug on
Debug
Protocol converter
Debug systems
Debug host Protocol converter Debug target
Debug host
Programming the debug unit
About the debug unit
Halting debug-mode debugging
Monitor debug-mode debugging
All other state information associated with the debug unit
Coprocessor registers summary
11.3.2 CP14 access permissions
Debug register interface
Coprocessor registers
Debug memory-mapped registers
Offset Register Access Mnemonic Description Hex Number
Memory-mapped registers
Instruction Mnemonic Description
Memory addresses for breakpoints and watchpoints
Privilege of memory access permission
Power domains
Effects of resets on debug registers
APB port access permissions
Other registers
External debug interface access permissions Registers
Lock
Other Debug registers
11.4.2 CP14 c0, Debug ID Register
Accessing debug registers
Debug register descriptions
6shows the CP14 debug register map
BRP
Debug ID Register functions
WRP
11.4.4 CP14 c0, Debug Self Address Offset Register
To use the Debug ID Register, read CP14 c0 with
11.4.3 CP14 c0, Debug ROM Address Register
To use the Debug ROM Address Register, read CP14 c0 with
Debug Self Address Offset Register functions
Debug Self Address Offset Register format
10 Debug Status and Control Register functions
11.4.5 CP14 c1, Debug Status and Control Register
Flag is set to 1 on entry to debug state
ARM
Execute ARM instruction enable bit
= disabled, this is the reset value
MOE
DTR access mode
Data Transfer Register
Reserved RAZ
Watchpoint Fault Address Register
12 Watchpoint Fault Address Register functions
Vector Catch Register
SVC
14 Debug State Cache Control Register functions
Bits Field Reset Description Value
Debug State Cache Control Register
Instruction Transfer Register
315 Reserved
Debug Run Control Register
15 Debug Run Control Register functions
Breakpoint Control Registers
Breakpoint Value Registers
17 Breakpoint Control Registers functions
BVR2220 Meaning
+0 is accessed
Corresponding instruction address breakpoint
18 Meaning of BVR bits
19 Watchpoint Value Registers functions Bits Description
Watchpoint Value Registers
Watchpoint Control Registers
20 Watchpoint Control Registers functions
11 Watchpoint Control Registers format
Operating System Lock Status Register
Accessed
21 OS Lock Status Register functions
Authentication Status Register
23 Prcr functions
Device Power-down and Reset Control Register
Device Power-down and Reset Status Register
= Dbgnopwrdwn is LOW. This is the reset value
24 Prsr functions
15 Prsr format
Processor ID Registers
Management registers
27 Claim Tag Set Register functions Bits Field Function
Claim Registers
Claim Tag Set Register
Lock Status Register
Lock Access Register
318 Reserved RAZ or Sbzp Claim tag clear Reset value is
Claim Tag Clear Register
30 Device Type Register functions
Device Type Register
Debug Identification Registers
Bits Value Description
32 Fields in the Peripheral Identification Registers
Field Size Description
33 Peripheral ID Register 0 functions
37 Peripheral ID Register 4 functions
34 Peripheral ID Register 1 functions
35 Peripheral ID Register 2 functions
36 Peripheral ID Register 3 functions
1022
1020
Component Identification Register
1021
Software debug event
Debug events
Watchpoint debug events
Halting debug event
Behavior of the processor on debug events
Debug event priority
Debug exception
Four CP15 registers that record abort information are
40shows the values in the link register after exceptions
Following sections describe
Effect of debug exceptions on CP15 registers and Wfar
Avoiding unrecoverable states
41 Read PC value after debug state entry
Debug state
Privilege on
Entering debug state
41 Read PC value after debug state entry Debug event
Behavior of the PC and Cpsr in debug state
Privilege
Accessing registers and memory
Executing instructions in debug state
Writing to the Cpsr in debug state
Exceptions in debug state
Coprocessor instructions
Effect of debug state on non-invasive debug
Effects of debug events on processor registers
Leaving debug state
Precise Data abort
Imprecise Data Abort
Imprecise Data Aborts on entry and exit from debug state
Sets the DSCR1 core restarted flag to
Cache coherency in debug state
Cache debug
This section describes cache debug. It consists
Cache pollution in debug state
External debug interface
APB signals
Miscellaneous debug signals
This section describes the miscellaneous debug signals
Non-invasive debug permitted
Authentication signals
Changing the authentication signals
42 Authentication signal restrictions Dbgen a
Issue an Instruction Synchronization Barrier ISB instruction
Example 11-1 Executing an ARM instruction through the ITR
Using the debug functionality
Debug communications channel
Rules for accessing the DCC
Example 11-4 Target to host data transfer host end
Software access to the DCC
Debugger access to the DCC
Example 11-5shows the code for host-to-target data transfer
Example 11-6 Polling the DCC host end
Programming breakpoints and watchpoints
This section describes the following operations
Programming simple breakpoints and the byte address select
Example 11-7 Setting a simple breakpoint
Setting a simple aligned watchpoint
Example 11-8 Setting a simple aligned watchpoint
Setting a simple unaligned watchpoint
Not required
Example 11-9 Setting a simple unaligned watchpoint
45shows some examples
Single-stepping
Example 11-11 Entering debug state
Debug state entry
Example 11-10 Single-stepping off an instruction
Example 11-12 Leaving debug state
Debug state exit
Example 11-13 Reading an ARM register
Accessing registers and memory in debug state
This section describes the following
Reading and writing registers through the DCC
Example 11-16shows the code for reading the Cpsr
Reading the PC in debug state
Example 11-15shows the code to read the PC
Reading the Cpsr in debug state
Example 11-17 Writing the Cpsr
Example 11-19 Checking for an abort after memory access
Reading memory
Example 11-18shows the code for reading a byte of memory
Example 11-21 Reading a word of memory
Example 11-20 Reading a block of bytes of memory
Fast register read/write
Example 11-22 Changing the DTR access mode
Example 11-23 Reading registers in stall mode
Example 11-24 Writing registers in stall mode
Example 11-25 Reading a block of words of memory
Fast memory read/write
Example 11-27 Reading a coprocessor register
Accessing coprocessor registers
11-70
Debugging systems with energy management capabilities
Emulating power down
11-72
FPU Programmer’s Model
About the VFPv3-D16 architecture
About the FPU programmer’s model
FPU functionality
FPU views of the register bank
General-purpose registers
1shows the VFP system registers in the Cortex-R4F FPU
System registers
VFPv3 architecture describes the following system registers
This is a change in VFPv3 compared to VFPv2
All hardware ID information is privileged access only
Fpsid is privileged access only
Mvfr registers are privileged access only
Rmode
Floating-Point Status and Control Register, Fpscr
Fpscr Register bit functions
DNM
DNM IXE RAZ UFE OFE DZE IOE IDC
Floating-Point Exception Register, Fpexc
LEN
IDE RAZ
MVFR0 Register bit functions
Media and VFP Feature Registers, MVFR0 and MVFR1
Floating-Point Exception Register bit functions
DEX
Full denormal arithmetic supported for VFP
MVFR1 Register bit functions
Default NaN mode
Full-compliance mode Flush-to-zero mode Default NaN mode
Full-compliance mode
Flush-to-zero mode
NaN handling
Compliance with the Ieee 754 standard
Complete implementation of the Ieee 754 standard
Ieee 754 standard implementation choices
CDP
Comparisons
Underflow
QNaN and SNaN handling
Exceptions
Integration Test Registers
About Integration Test Registers
Programming and reading Integration Test Registers
Software access using APB
Itmiscin
Register Itctrl
Itetmif
Itmiscout
1110
Processor integration testing
1312
Performing integration testing
Using the Integration Test Registers
Itetmif Register bit assignments Bits Name Function
Itetmif Register ETM interface
Itmiscout Register bit assignments Bits Name Function
Itmiscout Register Miscellaneous Outputs
Itmiscin Register Miscellaneous Inputs
Etmextout
Integration Mode Control Register Itctrl
Bits Name Function
Dbgrestart
Intmode
Bits Access Reset value Name Function
7shows the fields of the Itctrl Register
RAZ/SBZP
Multiplies on Divide on Branches on
Cycle Timings and Interlock Behavior
Dual issue on
Instruction execution overview
About cycle timings and interlock behavior
Definition of terms
Following sequence where R1 is a Late Reg takes two cycles
Flag-setting instructions
Conditional instructions
Assembler language syntax
Takes three cycles because of the result latency of R1
Register interlock examples
Instruction Behavior Sequence
Takes two cycles because there are no register dependencies
Cycle counts if destination is the PC
Data processing instructions
Cycle counts if destination is not PC
Register controlled shifts
Example interlocks
Shifter
QADD, QDADD, QSUB, and Qdsub instructions
SEL
Media data-processing
USAD8 instruction
Sum of Absolute Differences SAD
Instruction sequence Behavior
Result of the USAD8 instruction
Umlals
Multiplies
14-13
Divide
Example instruction Cycles Memory Comments
Branches
10 Branch instruction cycle timing behavior
All MSR instructions to the Spsr
Mode changing
Processor state updating instructions
All MRS instructions
13shows the cycle timing behavior for loads to the PC
Single load and store instructions
Example instruction Cycles Memory Result Comments Latency
Base register update
13 Cycle timing behavior for loads to the PC
14-19
Load and Store Double instructions
Register offset, then 3-issue cycles
Write-back
Load and Store Multiple instructions
Correct condition prediction and incorrect
Load Multiples, where the PC is in the register list
Correct condition prediction and correct
Return stack prediction
14-23
RFE and SRS instructions
Clrex
Synchronization instructions
Some instructions such as cache operations take more cycles
Coprocessor instructions
Prefetch Abort Undefined Instruction
SVC formerly SWI
Miscellaneous instructions
Serializing
Floating-point register transfer instructions
Blocking and serializing
2,2
Floating-point load/store instructions
Bit aligned address
Not aligned
4,5
2,3
Floating-point single-precision data processing instructions
Floating-point double-precision data processing instructions
Dual issue rules
Dual issue
Dual issue rules Permitted combinations on
28 Permitted instruction combinations
Dual issue First instruction Second instruction Case
Permitted combinations
Case F2Db
Case F2stb
Any single-precision CDPi, excluding
Multiply-accumulate instructionso
Processor timing on Processor timing parameters on
AC Characteristics
Processor timing
Clock uncertainty 50%
Processor timing parameters
Input port timing parameters
Clock uncertainty 10%
Clock uncertainty 60%
3shows the timing parameters for the interrupt input ports
4shows the input timing parameters for the AXI master port
Rreadys
5shows the input timing parameters for the AXI slave port
7shows the input timing parameters for the ETM input ports
6shows the input timing parameters for the debug input ports
Clock uncertainty 40%
8shows the timing parameters for the test input ports
Clock uncertainty 65%
11shows the timing parameters for the interrupt output ports
Output ports timing parameters
Write response channel Clock uncertainty 60%
13shows the timing parameters for the AXI slave output ports
BRESPS10
Clock uncertainty 45%
16shows the timing parameters for the test output ports
Fpidc
18shows the timing parameters for the FPU output signals
15-13
FPU signals on page A-23
Processor Signal Descriptions
From any clock
About the processor signal descriptions
Any
Signal Direction Clocking Description
Global signals
Table A-1 Global signals
Information
Configuration signals
Table A-2shows the processor configuration signals
Table A-2 Configuration signals
Tie High for odd parity
Tie LOW for even parity
RMWENRAM10b
Interrupt signals, including VIC interface signals
AXI master port
L2 interface signals
Table A-4 AXI master port signals for the L2 interface
Protection signals provide addition information about a bus
Identification tag for the write data group of signals
Identification tag for the write response signal
Identification tag for the read address group of signals
AXI slave port
AXI master port error detection signals
Table A-5 AXI master port error detection signals
Table A-6 AXI slave port signals for the L2 interface
One to 16. a four bit binary value minus one determines
Protection information, privileged/normal access. AWPROT0
AXI specification
Protection information, privileged/normal access. ARPROT0
Table A-7 AXI slave port error detection signals
AXI slave port error detection signals
ATCM, one hot. AWUSERS30 signal is not part
Standard AXI specification
Table A-9shows the B0TCM port signals
TCM interface signals
Table A-8shows the Atcm port signals
= DMA
Table A-10shows the B1TCM port signals
Table A-10 B1TCM port signals
Write parity or ECC code for B1TCM
B1TCM RAM access is sequential
Address for B1TCM data RAM
Write data for B1TCM data RAM
Table A-11 Dual core interface signals
Dual core interface signals
Table A-11shows the dual redundant core interface signals
Table A-12 Debug interface signals
Debug interface signals
Table A-13shows the debug miscellaneous signals
Input Tie-off Debug self-address offset valid
Table A-13 Debug miscellaneous signals
Input Tie-off Debug ROM physical address valid
Input Tie-off Debug self-address offset
Table A-14 ETM interface signals
ETM interface signals
Table A-14shows the ETM interface signals
Table A-15 Test signals
Test signals
Table A-15shows the test signals
Table A-16shows the Mbist signals
Mbist signals
Table A-17shows the validation signals
Validation signals
Table A-18 FPU signals
FPU signals
ECC scheme selection guidelines on page B-2
ECC Schemes
ECC scheme selection guidelines
Clarified little-endian format
NCPUHALT removed from timing diagram Added sections
Revisions
Clarified byte-invariant big-endian format
Change Location
Table C-1 Differences between issue B and issue C
No technical changes
Table C-2 Differences between issue C and issue D
Base register write-back
Glossary
Abort, and an internal or External Abort
See also Data Abort, External Abort and Prefetch Abort
See Advanced Microcontroller Bus Architecture
See also Advanced High-performance Bus
See Advanced High-performance Bus
That are divisible by four and two respectively
Completed transfer
Active read transaction
Active transfer
Active write transaction
Write ID width
Read ID width
Read issuing capability
Write ID capability
See also Beat
See also Burst
Bus
Accesses are expected to be word-aligned
Accessed in parallel during a cache look-up
See also Word-invariant
See also Dirty
See also Clean
See Embedded Trace Macrocell
Precision and the fraction is all zeros
An instruction that is architecturally Undefined
By individual implementations
Option chosen does not affect software compatibility
Result of attempting to access invalid instruction memory
Serviced while normal program execution is suspended
See also Halt mode
See Cold reset
See Boundary scan chain
Or equal to 1 and is not restricted to being a power of two
See Should Be One
See Should Be Zero
User trap handler is executed
See Debug test access port
Increment of +2
Destination precision
A processor
Expected behavior for an unaligned access
Bit for the exception is set
Processor-specific. a victim is also known as a cast out
Cache terminology diagram
