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11.5 Management registers

The Management Registers define the standardized set of registers that all CoreSight

components implement. This section describes these registers.

Table11-25 shows the contents of the Management Registers for the processor debug unit.

11.5.1 Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the

corresponding CP15 Main ID Register and Feature ID Registers. See Chapter4 System Control

Coprocessor for details about the information contained in these registers.

Table11-26 shows the offset value, register number, mnemonic, and description that are

associated with each Process ID Register.

Table11-25 Management Registers
Offset
(hex)
Register
number Access Mnemonic Description
0xD00-0xDFC
832-895 R - Processor Identifier Registers. See Processor ID Registers.
0xF00
960 RW ITCTRL Integration Mode Control Registers. See Integration Mode
Control Register (ITCTRL) on page13-9.
0xFA0
1000 CLAIMSET Claim Tag Set Register. See Claim Tag Set Register on
page11-33.
0xFA4
1001 CLAIMCLR Claim Tag Clear Register. See Claim Tag Clear Register on
page11-34.
0xFB0
1004 W LOCKACCESS Lock Access Register. See Lock Access Register on
page11-34.
0xFB4
1005 R LOCKSTATUS Lock Status Register. See Lock Status Register on
page11-34.
0xFB8
1006 R AUTHSTATUS Authentication Status Register. See Authentication Status
Register on page11-29.
0xFB8-0xFC4
1006-1009 R - Reserved.
0xFC8
1010 R DEVID Device Identifier. Reserved.
0xFCC
1011 R DEVTYPE Device Type Register. See Device Type Register on
page11-35.
0xFD0-0xFFC
1012-1023 R - Identification Registers. See Debug Identification
Registers on page11-35.
Table11-26 Processor Identifier Registers
Offset (hex) Register number Mnemonic Function
0xD00
832 MIDR Main ID Register
0xD04
833 CTR Cache Type Register
0xD08
834 TCMTR TCM Type Register
0xD0C
835 - Alias of MIDR