Processor Signal Descriptions

 

 

 

 

Table A-2 Configuration signals (continued)

 

 

 

 

Signal

Direction

Clocking

Description

 

 

 

 

CFGBTCMSZ[3:0]

Input

Tie-off

Selects the BTCM size. The encodings for the TCM sizes are:

 

 

 

b0000

= 0KB

 

 

 

b0011

= 4KB

 

 

 

b0100

= 8KB

 

 

 

b0101

= 16KB

 

 

 

b0110

= 32KB

 

 

 

b0111 = 64KB

 

 

 

b1000

= 128KB

 

 

 

b1001

= 256KB

 

 

 

b1010

= 512KB

 

 

 

b1011

= 1MB

 

 

 

b1100

= 2MB

 

 

 

b1101

= 4MB

 

 

 

b1110 = 8MB.

 

 

 

 

CFGNMFI

Input

Tie-off,

When HIGH, enable non-maskable Fast Interrupts. Reflected in

 

 

Reset

the NMFI bit. See c1, System Control Register on page 4-35for

 

 

 

more information.

 

 

 

 

ENTCM1IF

Input

Tie-off

Enable B1TCM interface.

 

 

 

Use B0TCM only if this signal not tied HIGH.

 

 

 

 

PARECCENRAM[2:0]

Input

Tie-off,

TCMs parity or ECC check enable. Tie each bit HIGH to enable

 

 

Reset

parity or ECC checking on the appropriate TCM at reset. Use

 

 

 

following values:

 

 

 

2:B1TCMa

 

 

 

1: B0TCMa

 

 

 

0: ATCM

 

 

 

See Auxiliary Control Registers on page 4-38for more

 

 

 

information.

 

 

 

 

PARLVRAM

Input

Tie-off,

Selects between odd and even parity for caches, TCMs, and

 

 

Reset

buses. See Chapter 8 Level One Memory System:

 

 

 

Tie LOW for even parity

 

 

 

Tie HIGH for odd parity.

ARM DDI 0363E

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Image 418
ARM R4F, r1p3 manual Tie LOW for even parity, Tie High for odd parity