ARM r1p3, R4, R4F

Debug

ID013010 Non-Confidential, Unrestricted Access

[8:5] Byte address

select

For breakpoints programmed to match an instruction address, the debugger must write a

word-aligned address to the BVR. You can then use this field to program the breakpoint so

it hits only if certain byte addresses are accessed.b

If the BRP is programmed for instruction address match:

b0000 = the breakpoint never hits

bxxx1 = the breakpoint hits if the byte at address (BVR &

0xFFFFFFFC

) +0 is accessed

bxx1x = the breakpoint hits if the byte at address (BVR &

0xFFFFFFFC

) +1 is accessed

bx1xx = the breakpoint hits if the byte at address (BVR &

0xFFFFFFFC

) +2 is accessed

b1xxx = the breakpoint hits if the byte at address (BVR &

0xFFFFFFFC

) +3 is accessed

b1111 = the breakpoint hits if any of the four bytes starting at address (BVR &

0xFFFFFFFC

)

+0 is accessed.

If the BRP is programmed for instruction address mismatch, the breakpoint hits where the

corresponding instruction address breakpoint does not hit, that is, the range of addresses

covered by an instruction address mismatch breakpoint is the negative image of the

corresponding instruction address breakpoint.

If the BRP is programmed for context ID comparison, this field must be set to b1111.

Otherwise, breakpoint and watchpoint debug events might not be generated as expected.

[4:3] Reserved -

[2:1] S Supervisor access control. The breakpoint can be conditioned on the mode of the processor:

b00 = User, System, or Supervisor

b01 = Privileged

b10 = User

b11 = any.

[0] B Breakpoint enable:

0 = Breakpoint disabled. This is the reset value.

1 = Breakpoint enabled.

a. If BCR[28:24] is not set to b00000, then BCR[8:5] must be set to b1111. Otherwis e the be havio r is Unp redict able. In addition,

if BCR[28:24] is not set to b00000, then the corresponding BVR bits that are not being included in the comparison Should Be

Zero. Otherwise the behavior is Unpredictable. If this BRP is programmed for context ID comparison, this field must be set

to b00000. Otherwise the behavior is Unpredictable. There is no encoding for a full 32-bit mask but the same effect of a break

anywhere breakpoint can be achieved by setting BCR[22] to 1 and BCR[8:5] to b0000.

b. Writing a value to BCR[8:5] so that BCR[8] is not equal to BCR[7] or BCR[6] is not equal to BCR[5] has Unpredictable

results.

Table11-18 Meaning of BVR bits [22:20]

BVR[22:20] Meaning

b000 The corresponding BVR[31:2] is compared against the instruction address bus and the state of the

processor against this BCR. It generates a breakpoint debug event on a joint instruction address and state

match.

b001 The corresponding BVR[31:2] is compared against the instruction address bus and the state of the

processor against this BCR. This BRP is linked with the one indicated by BCR[19:16] linked BRP field.

They generate a breakpoint debug event on a joint instruction address, context ID, and state match.

b010 The corresponding BVR[31:0] is compared against CP15 Context ID Register, c13 and the state of the

processor against this BCR. This BRP is not linked with any other one. It generates a breakpoint debug

event on a joint context ID and state match. For this BRP, BCR[8:5] must be set to b1111. Otherwise it

is Unpredictable whether a breakpoint debug event is generated.

Table11-17 Breakpoint Control Registers functions (continued)

Bits Field Function