ARM r1p3, R4F manual Program status registers, N, Z, C, and V bits

Programmer’s Model

2.7Program status registers

The processor contains one CPSR and five SPSRs for exception handlers to use. The program status registers:

•hold information about the most recently performed ALU operation

•control the enabling and disabling of interrupts

•set the processor operating mode.

Figure 2-4shows the bit arrangement in the status registers.

31 30 29 28 27 26 25 24 23 20 19 16 15 10 9 8 7 6 5 4 0

N Z C V Q

J

DNM

GE[3:0]

IT[7:2]

E A I

F T

M[4:0]

Greater than or equal to

Java state bit IT[1:0] Sticky overflow Overflow Carry/Borrow/Extend Zero Negative/Less than

Mode bits Thumb state bit FIQ disable IRQ disable

Imprecise abort disable bit

Data endianness bit

Figure 2-4 Program status register

The following sections explain the meanings of these bits:

•The N, Z, C, and V bits

•The Q bit on page 2-11

•The IT bits on page 2-11

•The J bit on page 2-12

•The DNM bits on page 2-12

•The GE bits on page 2-12

•The E bit on page 2-13

•The A bit on page 2-13

•The I and F bits on page 2-13

•The T bit on page 2-13

•The M bits on page 2-14

2.7.1The N, Z, C, and V bits

The N, Z, C, and V bits are the condition code flags. You can optionally set them with arithmetic and logical operations, and also with MSR instructions and MRC instructions to R15. The processor tests these flags in accordance with an instruction's condition code to determine whether to execute that instruction.

In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits. The exceptions are:

•BKPT

•CPS

•LDC2

•MCR2

•MCRR2

•MRC2

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