ARM R4F, r1p3 manual DTR access mode, Moe

Debug

			Table 11-10 Debug Status and Control Register functions (continued)
Bits	Field	Function
[5:2]	MOE	Method of entry bits:
		b0000 = a DRCR[0] halting debug event occurred
		b0001 = a breakpoint occurred
		b0100 = an EDBGRQ halting debug event occurred
		b0011 = a BKPT instruction occurred
		b1010 = a precise watchpoint occurred
		others = reserved.
		These bits are set to indicate any of:
		•	the cause of a debug exception
		•	the cause for entering debug state.
		A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status
		Register to determine whether a debug exception occurred and then use these bits to
		determine the specific debug event.
[1]a	Core restarted	Core restarted bit:
		0 = the processor is exiting debug state
		1 = the processor has exited debug state. This is the reset value.
		The debugger can poll this bit to determine when the processor responds to a request to
		leave debug state.
[0]a	Core halted	Core halted bit:
		0 = the processor is in normal state. This is the reset value.
		1 = the processor is in debug state.
		The debugger can poll this bit to determine when the processor has entered debug state.

a.These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DSCR[18] to a 0 and DSCR[1:0] to 10.

To use the Debug Status and Control Register, read or write CP14 c1 with:

MRC p14, 0, <Rd>, c0, c1, 0 ; Read Debug Status and Control Register

MCR p14, 0, <Rd>, c0, c1, 0 ; Write Debug Status and Control Register

DTR access mode

You can use the DTR access mode field to optimize data transfer between a debugger and the processor.

The DTR access mode can be one of the following:

•Nonblocking. This is the default mode.

•Stall.

•Fast.

In Non-blocking mode, reads from DTRTX and writes to DTRRX and ITR are ignored if the appropriate latched ready flag is not in the ready state. These latched flags are updated on DSCR reads. The following applies:

•writes to DTRRX are ignored if DTRRXfull_l is set to b1

•reads from DTRTX are ignored, and return an Unpredictable value, if DTRTXfull_l is set to b0

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	11-17
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