ARM R4 Components of the processor, This section describes the main components of the processor

Introduction

1.3Components of the processor

This section describes the main components of the processor:

•Data Processing Unit on page 1-5

•Load/store unit on page 1-5

•Prefetch unit on page 1-5

•L1 memory system on page 1-5

•L2 AXI interfaces on page 1-7

•Debug on page 1-8

•System control coprocessor on page 1-9

•Interrupt handling on page 1-9.

Figure 1-1shows the structure of the processor.

		ETM		Debug
	Processor
		ETM		Debug
		interface		interface
			Data	Load/Store
		Prefetch Unit	Processing
				Unit
			Unit
			Level one memory system
		L1	Memory	L1
		instruction	Protection	data cache
ATCM	Tightly-	cache control	Unit	control
B1TCM	Coupled
	Memory
B0TCM	(TCM)	L1		L1
	interface
		instruction		data
		cache RAM		cache RAM
		L2 interface	Level two interface	L2 interface
		AXI		AXI
		slave port		master port

AXI slave bus AXI master bus

Figure 1-1 Processor block diagram

The PreFetch Unit (PFU) fetches instructions from the memory system, predicts branches, and passes instructions to the Data Processing Unit (DPU). The DPU executes all instructions and uses the Load/Store Unit (LSU) for data memory transfers. The PFU and LSU interface to the L1 memory system that contains L1 instruction and data caches and an interface to a L2 system. The L1 memory can also contain optional TCM interfaces.

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