ARM r1p3, R4, R4F - page 424

Processor Signal Descriptions
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AWBURSTS[1:0] Input CLKIN Write burst type.
AWIDS[7:0] Input CLKIN The identification tag for the write address group of signals.
AWLENS[3:0] Input CLKIN Write transfer burst length. The transfer burst length range is from
one to 16. A four bit binary value minus one determines the
transfer burst length.
AWPR OTS Input CLKIN Protection information, privileged/normal access. AWP R O T [ 0 ] in
AXI specification.
AWREADYS Output CLKIN Address ready. The slave uses this signal to indicate that it can
accept the address.
AWSIZES[2:0] Input CLKIN Indicates the size of the transfer.
AWUSERS[3:0] Input CLKIN Memory type select data cache, instruction cache, BTCM or
ATCM, one hot. AWUSE R S [ 3 : 0 ] signal is not part of the standard
AXI specification.
AWVAL I D S Input CLKIN Indicates address and control are valid.
Write Data Channel
WDATAS[63:0] Input CLKIN Write data.
WLASTS Input CLKIN Indicates the last data transfer of a burst.
WREADYS Output CLKIN Indicates that the slave is ready to accept write data.
WSTRBS[7:0] Input CLKIN Write strobes used to indicate which byte lanes must be updated.
WVALIDS Input CLKIN Indicates address and control are valid.
Write Response Channel
BIDS[7:0] Output CLKIN The identification tag for the write response signal.
BREADYS Input CLKIN Indicates that the core is ready to accept write response.
BRESPS[1:0] Output CLKIN Write response.
BVALIDS Output CLKIN Indicates that a valid write response is available.
Read Address Channel
ARADDRS[22:0] Input CLKIN Instruction fetch burst start address.
ARBURSTS[1:0] Input CLKIN Burst type.
ARIDS[7:0] Input CLKIN Identification tag for the read address group of signals.
ARLENS[3:0] Input CLKIN Instruction fetch burst length.
ARPROTS Input CLKIN Protection information, privileged/normal access. ARPROT[0] in
AXI specification.
ARREADYS Output CLKIN Address ready. The slave uses this signal to indicate that it can
accept the address.
ARSIZES[2:0] Input CLKIN Indicates the size of the transfer.
TableA-6 AXI slave port signals for the L2 interface (continued)
Signal Direction Clocking Description