ARM R4F, r1p3 About the events, Event bus interface bit functions, Bit position Update Value

Events and Performance Monitor

6.1About the events

The processor includes logic to detect various events that can occur, for example, a cache miss. These events provide useful information about the behavior of the processor that you can use when debugging or profiling code.

The events are made visible on an output bus, EVNTBUS, and can be counted using registers in the Performance Monitoring Unit (PMU). See Event bus interface on page 6-19for more information about the event bus, and About the PMU on page 6-6for more information about the PMU. Table 6-1lists the events that are generated, along with the bit position of each event on the event bus, and the numbers that the PMU uses to refer the events. Event reference numbers that are not listed are Reserved. See Error detection events on page 8-36for more information on the CFLR related events.

	Table 6-1 Event bus interface bit functions
EVNTBUS	Description	CFLR	Event
			Ref.
bit position		update
			Value
N/A	Software increment. The register is incremented only on writes to the	-	0x00
	Software Increment Register. See c9, Software Increment Register on
	page 6-11.
[0]	Instruction cache miss.	-	0x01
	Each instruction fetch from normal Cacheable memory that causes a refill
	from the level 2 memory system generates this event. Accesses that do not
	cause a new cache refill, but are satisfied from refilling data of a previous miss
	are not counted. Where instruction fetches consist of multiple instructions,
	these accesses count as single events. CP15 cache maintenance operations do
	not count as events.
[1]	Data cache miss.	-	0x03
	Each data read from or write to normal Cacheable memory that causes a refill
	from the level 2 memory system generates this event. Accesses that do not
	cause a new cache refill, but are satisfied from refilling data of a previous miss
	are not counted. Each access to a cache line to normal Cacheable memory that
	causes a new linefill is counted, including the multiple transactions of an LDM
	and STM. Write-through writes that hit in the cache do not cause a linefill and
	so are not counted. CP15 cache maintenance operations do not count as
	events.
[2]	Data cache access.	-	0x04
	Each access to a cache line is counted including the multiple transactions of
	an LDM, STM, or other operations. CP15 cache maintenance operations do not
	count as events.
[3]	Data Read architecturally executed.	-	0x06
	This event occurs for every instruction that explicitly reads data, including
	SWP.
[4]	Data Write architecturally executed.	-	0x07
	This event occurs for every instruction that explicitly writes data, including
	SWP.
[5]	Instruction architecturally executed.	-	0x08
[6]	Dual-issued pair of instructions architecturally executed.	-	0x5e
[7]	Exception taken.	-	0x09
	This event occurs on each exception taken.

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