ARM R4F, r1p3 manual Debug Identification Registers, Device Type Register functions

Debug

Table 11-29shows how the bit values correspond with the Lock Status Register functions.

			Table 11-29 Lock Status Register functions
Bits	Field	Function
[31:3]	Reserved	Do not modify on writes. On reads, the value returns zero.
[2]	32-bit access	Indicates that a 32-bit access is required to write the key to the Lock Access Register.
		This bit always reads 0.
[1]	Locked bit	Locked bit:
		0	= Writes are permitted.
		1	= Writes are ignored. This is the reset value.
[0]	Lock implemented bit	Indicates that the OS lock functionality is implemented. This bit always reads 1.

11.5.5Device Type Register

The Device Type Register is a read-only register that indicates the type of debug component. Figure 11-19shows the bit arrangement of the Device Type Register.

31 8 7 4 3 0

Reserved

Sub type

Main class

Figure 11-19 Device Type Register format

Table 11-30shows how the bit values correspond with the Device Type Register functions.

		Table 11-30 Device Type Register functions
Bits	Field	Function
[31:8]	Reserved	Do not modify on writes. On reads, the value returns zero.
[7:4]	Subtype	0x1, indicates that the sub-type of the device is processor core.
[3:0]	Main class	0x5, indicates that the main class of the device is debug logic.

11.5.6Debug Identification Registers

The Debug Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information that all CoreSight components require. Only bits [7:0] of each register are used. The remaining bits Read-As-Zero.

The Component Identification Registers identify the processor as a CoreSight component. Only bits [7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

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