ARM r1p3, R4, R4F 12.1 About the FPU programmers model

FPU Programmer’s Model

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12.1 About the FPU programmer’s model

The FPU implements the VFPv3-D16 architecture and the Common VFP Sub-Architecture v2.

This includes the instruction set of the VFPv3 architecture. See the ARM Architecture Reference

Manual for information on the VFPv3 instruction set.

12.1.1 FPU functionality

The FPU is an implementation of the ARM Vector Floating Point v3 architecture, with 16

double-precision registers (VFPv3-D16). It provides floating-point computation functionality

that is compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point

Arithmetic, referred to as the IEEE 754 standard. The FPU supports all data-processing

instructions and data types in the VFPv3 architecture as described in the ARM Architecture

Reference Manual.

The FPU fully supports single-precision and double-precision add, subtract, multiply, divide,

multiply and accumulate, and square root operations. It also provides conversions between

fixed-point and floating-point data formats, and floating-point constant instructions. The FPU

does not support any data processing operations on vectors in hardware. Any data processing

instruction that operates on a vector generates an UNDEFINED exception. The operation can

then be emulated in software if necessary.

12.1.2 About the VFPv3-D16 architecture

The VFPv3-D16 architecture only includes 16 double-precision registers. VFPv3 includes 32

double-precision registers by default. An instruction which attempts to access any of the

registers D16-D31 generates an UNDEFINED exception.