ARM R4F, r1p3 manual Cache RAM organization, Tag RAM, Dirty RAM on Data RAM on

Level One Memory System

Any uncorrectable errors found cause an imprecise abort. An imprecise abort can also be raised on a correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register.

Any detected error is signaled with the appropriate event.

8.5.4Cache RAM organization

This section describes RAM organization in the following sections:

•Tag RAM

•Dirty RAM on page 8-27

•Data RAM on page 8-27.

Tag RAM

The tag RAMs consist of four ways of up to 512 lines. The width of the RAM depends on the build options selected, and the size of the cache. The following tables show the tag RAM bits:

•Table 8-4shows the tag RAM bits when parity is implemented

•Table 8-5shows the tag RAM bits when ECC is implemented

•Table 8-6shows the tag RAM bits when neither parity nor ECC is implemented.

Table 8-4 Tag RAM bit descriptions, with parity

Bit in the tag cache line	Description
Bit [23]	Parity bit
Bit [22]	Valid bit
Bits [21:0]	Tag value

Table 8-5 Tag RAM bit descriptions, with ECC

Bit in the tag cache line	Description
Bits [29:23]	ECC code bits
Bit [22]	Valid bit
Bits [21:0]	Tag value

Table 8-6 Tag RAM bit descriptions, no parity or ECC

Bit in the tag cache line	Description
Bit [22]	Valid bit
Bits [21:0]	Tag value

A cache line is marked as valid by bit [22] of the tag RAM. Each valid bit is associated with a whole cache line, so evictions always occur on the entire line.

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