ARM r1p3, R4F manual C0, Instruction Set Attributes Registers

			System Control Coprocessor
		Table 4-18 Instruction Set Attributes Register 4 bit functions (continued)
Bits	Field	Function
[15:12]	SMC instructions	Indicates support for Secure Monitor Call (SMC) (formerly SMI) instructions.
		0x0, no support.
[11:8]	Write-back instructions	Indicates support for write-back instructions.
		0x1, supports all the writeback addressing modes defined in ARMv7.
[7:4]	With shift instructions	Indicates support for with-shift instructions.
		0x4, the processor supports:
		•	the full range of constant shift options, on load/store and other instructions
		•	register-controlled shift options.
[3:0]	Unprivileged instructions	Indicates support for Unprivileged instructions.
		0x2, the processor supports LDR{SBBSHH}T and STR{BH}T.

To access the Instruction Set Attributes Register 4 read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 4 ; Read Instruction Set Attributes Register 4

c0, Instruction Set Attributes Registers 5-7

The Instruction Set Attributes Registers 5-7 provide additional information about the properties of the processor.

The Instruction Set Attributes Register 5 is:

•a read-only register

•accessible in Privileged mode only.

In the processor, Instruction Set Attributes Register 5 is read as 0x00000000.

To access the Instruction Set Attributes Register 5, read CP15 with:

MRC p15, 0, <Rd>, c0, c2, 5 ; Read Instruction Set Attribute Register 5

Instruction Set Attributes Registers 6 and 7 are not implemented, and their positions in the register map are Reserved. They correspond to CP15 accesses with:

MRC p15, 0, <Rd>, c0, c2, 6 ; Read Instruction Set Attribute Register 6

MRC p15, 0, <Rd>, c0, c2, 7 ; Read Instruction Set Attribute Register 7

These registers are read-only, and are accessible in Privileged mode only.

4.2.12c0, Current Cache Size Identification Register

The Current Cache Size Identification Register provides the current cache size information for the instruction and data caches. Architecturally, there can be up to eight levels of cache, containing instruction, data, or unified caches. This processor contains L1 instruction and data caches. The Cache Size Selection Register determines which Current Cache Size Identification Register to select, see c0, Cache Size Selection Register on page 4-35.

The Current Cache Size Identification Register is:

•a read-only register

•accessible in Privileged mode only.

Figure 4-24 on page 4-33shows the bit arrangement for the Current Cache Size Identification Register.

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