ARM R4F, r1p3 manual C15, nVAL FIQ Enable Set Register, Ccnt overflow FIQ request

System Control Coprocessor

On reads, this register returns the current setting. On writes, interrupt requests can be enabled. If an interrupt request has been enabled it is disabled by writing to the nVAL IRQ Enable Clear Register, see c15, nVAL IRQ Enable Clear Register on page 4-65.

If one or more of the IRQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an IRQ request is indicated by nVALIRQ being asserted LOW. This signal might be passed to a system interrupt controller.

c15, nVAL FIQ Enable Set Register

The nVAL FIQ Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate an fast interrupt request on overflow. If enabled, the interrupt request is signaled by nVALFIQ being asserted LOW.

The nVAL FIQ Enable Set Register is:

•A read/write register.

•Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register on page 6-15.

Figure 4-45shows the bit arrangement for the nVAL FIQ Enable Set Register.

31

C

3 2 1 0

Reserved

Cycle count overflow FIQ request enable P2

Performance monitor counter

overflow FIQ request enables

P1

P0

Figure 4-45 nVAL FIQ Enable Set Register format

Table 4-43shows how the bit values correspond with the nVAL FIQ Enable Set Register.

Table 4-43 nVAL FIQ Enable Set Register bit functions

Bits	Field	Function
[31]	C	CCNT overflow FIQ request
[30:3]	Reserved	UNP or SBZP
[2]	P2	PMC2 overflow FIQ request
[1]	P1	PMC1 overflow FIQ request
[0]	P0	PMC0 overflow FIQ request

To access the FIQ Enable Set Register, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c1, 1 ; Read FIQ Enable Set Register

MCR p15, 0, <Rd>, c15, c1, 1 ; Write FIQ Enable Set Register

On reads, this register returns the current setting. On writes, interrupt requests can be enabled. If an interrupt request has been enabled it is disabled by writing to the FIQ Enable Clear Register, see c15, nVAL FIQ Enable Clear Register on page 4-66.

If one or more of the FIQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an FIQ request is indicated by nVALFIQ being asserted LOW. This signal can be passed to a system interrupt controller.

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