ARM R4F, r1p3 manual Arm, Execute ARM instruction enable bit, = disabled, this is the reset value

Debug

			Table 11-10 Debug Status and Control Register functions (continued)
Bits	Field	Function
[13]	ARM	Execute ARM instruction enable bit:
		0	= disabled, this is the reset value
		1	= enabled.

If this bit is set and an ITR write succeeds, the processor fetches an instruction from the ITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable.

[12]	Comms	CP14 debug user access disable control bit:
		0	= CP14 debug user access enable, this is the reset value
		1	= CP14 debug user access disable.
		If this bit is set and a User mode process attempts to access any CP14 debug registers, an
		Undefined instruction exception is taken.
[11]	IntDis	Interrupts disable bit:
		0	= interrupts enabled, this is the reset value
		1	= interrupts disabled.
		If this bit is set, the IRQ and FIQ input signals are inhibited. The external debugger can
		optionally use this bit to execute pieces of code in normal state as part of the debugging
		process to avoid having an interrupt taking control of the program flow. For example, the
		debugger might use this bit to execute an OS service routine to bring a page from disk into
		memory. It might be undesirable to service any interrupt during the routine execution.
[10]	DbgAck	DbgAck bit. If this bit is set to 1, the DBGACK output signal is forced HIGH, regardless
		of the processor state. The external debugger can optionally use this bit to execute pieces
		of code in normal state as part of the debugging process for the system to behave as if the
		processor is in debug state. Some systems rely on DBGACK to determine whether data
		accesses are application or debugger generated. This bit is 0 on reset.
[9]	Reserved	RAZ on reads, SBZP on writes.
[8]	Sticky Undefined	Sticky Undefined bit:
		0 = no Undefined exception occurred in debug state since the last time this bit was cleared
		1	= an Undefined exception occurred while in debug state since the last time this bit was
		cleared.
		This flag detects Undefined exceptions generated by instructions issued to the processor
		through the ITR. This bit is set to 1 when an Undefined instruction exception occurs while
		the processor is in debug state and is cleared by writing a 1 to DRCR[2].
[7]	Sticky imprecise	Sticky imprecise Data Abort bit:
	abort	0	= no imprecise Data Aborts occurred since the last time this bit was cleared
		1	= an imprecise Data Abort occurred since the last time this bit was cleared.
		This flag detects imprecise Data Aborts triggered by instructions issued to the processor
		through the ITR. This bit is set to 1 when an imprecise Data Abort occurs while the
		processor is in debug state and is cleared by writing a 1 to DRCR[2].
[6]	Sticky precise	Sticky precise Data Abort bit:
	abort	0	= no precise Data Abort occurred since the last time this bit was cleared
		1	= a precise Data Abort occurred since the last time this bit was cleared.

This flag detects precise Data Aborts generated by instructions issued to the processor through the ITR. This bit is set to 1 when a precise Data Abort occurs while the processor is in debug state and is cleared by writing to the DRCR[2].

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