ARM R4F, r1p3 manual See Embedded Trace Macrocell

		Glossary
Enabled exception	An exception is enabled when its exception enable bit in the FPCSR is set. When an enabled
	exception occurs, a trap to the user handler is taken. An operation that generates an exception
	condition might bounce to the support code to produce the result defined by the IEEE 754
	standard. The exception is then reported to the user trap handler.
Endianness	Byte ordering. The scheme that determines the order in which successive bytes of a data word
	are stored in memory. An aspect of the system’s memory mapping.
	See also Little-endian and Big-endian
ETM	See Embedded Trace Macrocell.
Event	1.	(Simple) An observable condition that can be used by an ETM to control aspects of a
		trace.
	2.	(Complex) A boolean combination of simple events that is used by an ETM to control
		aspects of a trace.
Exception	A fault or error event that is considered serious enough to require that program execution is
	interrupted. Examples include attempting to perform an invalid memory access, external
	interrupts, and Undefined instructions. When an exception occurs, normal program flow is
	interrupted and execution is resumed at the corresponding exception vector. This contains the
	first instruction of the interrupt handler to deal with the exception.
Exception service routine	See Interrupt handler.
Exception vector	See Interrupt vector.
Exponent	The component of a floating-point number that normally signifies the integer power to which
	two is raised in determining the value of the represented number.
External Abort	An indication from an external memory system to a core that the value associated with a
	memory access is invalid. An external abort is caused by the external memory system as a result
	of attempting to access invalid memory.
	See also See also Abort, Data Abort and Prefetch Abort
Halfword	A 16-bit data item.
Halt mode	One of two mutually exclusive debug modes. In halt mode all processor execution halts when a
	breakpoint or watchpoint is encountered. All processor state, coprocessor state, memory and
	input/output locations can be examined and altered by the JTAG interface.
	See also Monitor mode.
High vectors	Alternative locations for exception vectors. The high vector address range is near the top of the
	address space, rather than at the bottom.
Hit-Under-Miss (HUM)	A buffer that enables program execution to continue, even though there has been a data miss in
	the cache.
Host	A computer that provides data and other services to another computer. Especially, a computer
	providing debugging services to a target being debugged.
HUM	See Hit-Under-Miss.
IEEE 754 standard	IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. The standard
	that defines data types, correct operation, exception types and handling, and error bounds for
	floating-point systems. Most processors are built in compliance with the standard either in
	hardware or in a combination of hardware and software.

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