Cycle Timings and Interlock Behavior

14.23.2 Permitted combinations

Table 14-28lists the permitted instruction combinations. Any instruction can be conditional or flag-setting unless otherwise stated. Only the exact instruction combinations listed in

Table 14-28can be dual issued, provided you ensure the instruction combinations obey the rules specified in Dual issue rules on page 14-34.

 

 

Table 14-28 Permitted instruction combinations

 

 

 

Dual issue

First instruction

Second instruction

case

 

 

Case A

Any instruction other than load/store multiple/double,

 

flag-setting multiply, non-VFP coprocessor operations,

 

miscellaneous processor control instructionsa, or floating

 

point instructions if floating point logic is not included in

 

the processor

B#immed

IT NOP

Case A-Fb

Any floating point instructions, excluding load/store

 

multiple, double precision CDP instructions, VCVT.F64.F32,

 

and VMRS and VMSR.

Case B1

LDR <Rt>, [<Rn>,

#<imm>]c

 

LDR <Rt>,

[<Rn>,

<Rm>]c

 

LDR <Rt>,

[<Rn>,

<Rm>, LSL #1, 2 or 3]c

Case B1-Fb

Any data processing instruction that does not require a shift by a register value.d

Any bitfield, saturate or bit-packing instruction.e

Any signed or unsigned extend instruction.f Any SIMD add or subtract instruction.g Other miscellaneous instructions.h

Any single-precision CDPi, excluding "VMOV.F32 <Sd>, #<imm>", VNEG.F32, VABS.F32, VCVT.F64.F32, VDIV.F32, and VSQRT.F32.

32-bit transfers to and from the floating-point register filel.

Case B2

STR <Rt>, [<Rn>, #<imm>]c

As for Case B1.

Case B2-Fb

 

As for Case B1-F

Case C

MOV <Rd>, #immedjk

Any data processing instruction.d

 

MOVW <Rd>, #immedj

Any bitfield, saturate or bit-packing

 

j

instruction.e

 

MOV <Rd>, <Rm>

 

 

 

Any signed or unsigned extend instruction.f

 

 

Any SIMD add or subtract instruction.g

 

 

Other miscellaneous instructions.h

Case C-Fb

 

32-bit transfers to and from the floating-point

 

 

register filel.

Case F1b,m

Any single-precision CDPi, excluding "VMOV.S32 <Sd>,

As for case C or C-F.

 

#<imm>", VCVT.F64.F32, VABS.F32, and VNEG.F32.

 

 

 

 

Case F2_ldb

VLDR.F32n

As for Case B1 or Case B1-F

ARM DDI 0363E

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14-35

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ARM R4F Permitted combinations, Permitted instruction combinations, Dual issue First instruction Second instruction Case