ARM R4F, r1p3 manual Taking an exception, Leaving an exception

Programmer’s Model

b.The return instruction you must use after an UNDEF exception has been handled depends on whether you want to retry the undefined instruction or not and, if so, on the size of the undefined instruction.

Taking an exception

When taking an exception the processor:

1.Preserves the address of the next instruction in the appropriate LR. When the exception is taken from:

ARM state

The processor writes the address of the instruction into the LR, offset by a value (current IA + 4 or IA + 8 depending on the exception) that causes the program to resume from the correct place on return.

Thumb state

The processor writes the address of the instruction into the LR, offset by a value (current IA + 2, IA + 4 or IA + 8 depending on the exception) that causes the program to resume from the correct place on return.

2.Copies the CPSR into the appropriate SPSR. Depending on the exception type, the processor might modify the IT execution state bits of the CPSR prior to this operation to facilitate a return from the exception.

3.Forces the CPSR mode bits to a value that depends on the exception and clears the IT execution state bits in the CPSR.

4.Sets the E bit based on the state of the EE bit. Both these bits are contained in the System Control Register, see c1, System Control Register on page 4-35.

5.The T bit is set based on the state of the TE bit.

6.Forces the PC to fetch the next instruction from the relevant exception vector.

The processor can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions.

Leaving an exception

When an exception has completed, the exception handler must move the LR, minus an offset, to the PC. The offset varies according to the type of exception, as Table 2-4 on page 2-16shows.

Typically the return instruction is an arithmetic or logical operation with the S bit set and Rd = R15, so the processor copies the SPSR back to the CPSR. Alternatively, an LDM ..,{..pc}^ or RFE instruction can perform a similar operation if the return state has been pushed onto a stack.

Note

The action of restoring the CPSR from the SPSR:

•Automatically restores the T, E, A, I, and F bits to the value they held immediately prior to the exception.

•Normally resets the IT execution state bits to the values held immediately prior to the exception. If the exception handler wants to return to the following instruction, these bits might require to be manually advanced to avoid applying the incorrect condition codes to that instruction. For more information about the IT instruction and Undefined instruction, and an example of the exception handler code, see the ARM Architecture Reference Manual.

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