ARM r1p3, R4F manual BRESPS10

AC Characteristics

Table 15-13 AXI slave output ports timing parameters (continued)

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	60%	BRESPS[1:0]
Clock uncertainty	60%	BVALIDS
Clock uncertainty	60%	ARREADYS
Clock uncertainty	60%	RIDS[7:0]
Clock uncertainty	60%	RDATAS[63:0]
Clock uncertainty	60%	RRESPS[1:0]
Clock uncertainty	60%	RLASTS
Clock uncertainty	60%	RVALIDS
Clock uncertainty	60%	BPARITYS
Clock uncertainty	60%	RPARITYS
Clock uncertainty	50%	AXISPARERR[2:0]

Table 15-14shows the timing parameters for the debug interface output ports.

Table 15-14 Debug interface output ports timing parameters

Output delay	Output delay	Signal name
minimum	maximum
Clock uncertainty	50%	PRDATADBG[31:0]
Clock uncertainty	50%	PREADYDBG
Clock uncertainty	50%	PSLVERRDBG
Clock uncertainty	50%	DBGNOPWRDWN
Clock uncertainty	50%	DBGACK
Clock uncertainty	50%	DBGTRIGGER
Clock uncertainty	50%	DBGRESTARTED
Clock uncertainty	50%	DBGRSTREQ
Clock uncertainty	50%	COMMTX
Clock uncertainty	50%	COMMRX

ARM DDI 0363E	Copyright © 2009 ARM Limited. All rights reserved.	15-10
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