ARM R4 Eviction buffer, Memory attributes, Arcachem and Awcachem encodings Encoding a Meaning

Level Two Interface

9.2.4Eviction buffer

As soon as a linefill is requested, the selected evicted cache line is loaded into the EViction

Buffer (EVB). The EVB forwards this information to the AXI bus when possible.

The EVB has a structure of 256 bits for data and 32 bits for the address. See Cache line write-back (eviction) on page 9-13for details of the AXI transaction generated.

The EVB is removed if cache RAMs are not implemented for the processor.

9.2.5Memory attributes

The Cortex-R4 AXI master interface uses the ARCACHEM, AWCACHEM, ARUSERM, and AWUSERM signals to indicate the memory attributes of the transfer, as returned by the MPU. Table 9-2Shows the encodings used for the signals ARCACHEM and AWCACHEM of the master interface. These are generated from the memory type and outer region attributes.

Table 9-2 ARCACHEM and AWCACHEM encodings

Encodinga	Meaning
b0000	Strongly Ordered
b0001	Device
b0011	Non-cacheable
b0110	Cacheable, write-through, allocate on reads only
b0111	Cacheable, write-back, allocate on reads only
b1111	Cacheable write-back, allocate on reads and writes

a. All encodings not shown in the table are reserved.

Table 9-3shows the encodings the master interface uses for the ARUSERM and AWUSERM signals. These are generated from the memory type and inner region attributes.

	Table 9-3 ARUSERM and AWUSERM encodings
Encodinga	Meaning
b00001	Strongly Ordered
b00010	Device, Non-shared
b00011	Device, shared
b00110	Non-cacheable, Non-shared
b00111	Non-cacheable, shared
b01100	Cacheable, write-through, read-allocate only, Non-shared
b01101	Cacheable, write-through, read-allocate only, shared
b11110	Cacheable, write-back, read- and write-allocate, Non-shared
b11111	Cacheable, write-back, read- and write-allocate, shared

a. All encodings not shown in the table are reserved.

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