ARM r1p3, R4 37shows the cache sizes and the resultant bit range for Set, Address format, 4KB 8KB

System Control Coprocessor

31 30 29 S+5 S+4 5 4 0

Way

Reserved

Set

Reserved

Figure 4-39 c7 format for Set and Way

Table 4-36shows how the bit values correspond with the Cache Operation functions for Set and Way format operations.

		Table 4-36 Functional bits of c7 for Set and Way
Bits	Field	Function
[31:30]	Way	Indicates the cache way to invalidate or clean.
[29:S+5]	Reserved	SBZ.
[S+4:5]	Set	Indicates the cache set to invalidate or clean. Because the cache sizes are configurable, the width
		of the Set field is unique to the cache size. See Table 4-37.
[4:0]]	Reserved	SBZ.

Table 4-37shows the cache sizes and the resultant bit range for Set.

Table 4-37 Widths of the set field for L1 cache sizes

Size	Set
4KB	[9:5]
8KB	[10:5]
16KB	[11:5]
32KB	[12:5]
64KB	[13:5]

See c0, Cache Type Register on page 4-15for more information on cache sizes.

Address format

Figure 4-40shows the address format for invalidate and clean operations.

31 5 4 0

Address

Reserved

Figure 4-40 Cache operations address format

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