ARM r1p3 To access the Processor Feature Register 1 read CP15 with, 8 c0, Debug Feature Register

		System Control Coprocessor
	Table 4-8 Processor Feature Register 1 bit functions (continued)
Bits	Field	Function
[11:8]	Microcontroller programmer’s model	Indicates support for Microcontroller programmer’s model:
		0x0, no support.
[7:4]	Security extension	Indicates support for Security Extensions Architecture:
		0x0, no support.
[3:0]	ARMv4 Programmer’s model	Indicates support for standard ARMv4 programmer’s model:
		0x1, the processor supports the ARMv4 model.

To access the Processor Feature Register 1 read CP15 with:

MRC p15, 0, <Rd>, c0, c1, 1 ; Read Processor Feature Register 1

4.2.8c0, Debug Feature Register 0

The Debug Feature Register 0 provides information about the debug system for the processor.

Debug Feature Register 0 is:

•a read-only register

•accessible in Privileged mode only.

Figure 4-14shows the bit arrangement for Debug Feature Register 0.

31 24 23 20 19 16 15 12 11 8 7 4 3 0

Reserved

Microcontroller debug model – memory mapped

Trace debug model – memory mapped

Trace debug model – coprocessor

Core debug model – memory mapped

Secure debug model

Core debug model – coprocessor

		Figure 4-14 Debug Feature Register 0 format
	Table 4-9shows how the bit values correspond with the Debug Feature Register 0 functions.
		Table 4-9 Debug Feature Register 0 bit functions
Bits	Field	Function
[31:24]	Reserved	SBZ.
[23:20]	Microcontroller	Indicates support for the microcontroller debug model - memory mapped:
	Debug model -	0x0, no support.
	memory mapped
[19:16]	Trace debug model -	Indicates support for the trace debug model - memory mapped:
	memory mapped	0x1, trace supported, memory mapped access.
[15:12]	Trace debug model -	Indicates support for the trace debug model - coprocessor:
	coprocessor	0x0, no support.

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