ARM R4F, r1p3 Power domains, Effects of resets on debug registers, APB port access permissions

Debug

The Watchpoint Fault Address Register (WFAR) reads an address and a processor state dependent offset, +8 for ARM and +4 for Thumb.

11.3.6Power domains

The processor has a single power domain. Therefore, it does not support the Event Catch

Register, the OS Lock, or the OS Save and Restore functionality.

11.3.7Effects of resets on debug registers

The processor has two reset signals which affect the debug registers in the following ways:

nSYSPORESET

You must assert this signal when powering up to set the non-debug processor logic to a known state.

PRESETDBGn

You can assert this signal to set all of the debug logic to a known state, without affecting the state of the remainder of the processor logic.

11.3.8APB port access permissions

The restrictions for accessing the APB slave port are described as follows:

Privilege of memory access

You must configure the system to disable accesses to the memory-mapped registers based on the privilege of the memory access.

Power down

The processor only supports a single power domain, therefore you must configure the system to return an error response to all accesses made to the APB interface while the processor is powered-down.

Privilege of memory access permission

When non-privileged software attempts to access the APB slave port, the system must ignore the access or generate an error response to the access. You must implement this restriction at the system level because the APB protocol does not have a privileged or user control signal. You can choose to have the system either ignore the access or generate an error response.

You can place additional restrictions on memory transactions that are permitted to access the APB port. However, ARM does not recommend this.

Locks permission

You can lock the APB slave port so that access to some debug registers is restricted. ARM

Architecture v7 defines two locks:

Software lock

The external debugger can set this lock to prevent software from modifying the debug registers settings. A debug monitor can also set this lock prior to returning control to the application to reduce the chance of erratic code changing the debug settings. When this lock is set, writes to all debug registers are ignored, except those generated by the external debugger, which override the lock. For more information, see Lock Access Register on page 11-34.

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