CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A

There is no specific timing requirement that should be met for asserting PKTEND pin to asserting SLWR. PKTEND can be asserted with the last data value clocked into the FIFOs or there- after. The setup time tSPE and the hold time tPEH must be met.

Although there are no specific timing requirements for the PKTEND assertion, there is a specific corner case condition that needs attention while using the PKTEND to commit a one byte or word packet. There is an additional timing requirement that needs to be met when the FIFO is configured to operate in auto mode and it is required to send two packets back to back: a full packet (full defined as the number of bytes in the FIFO meeting the level set in AUTOINLEN register) committed automatically followed by a short one byte or word packet committed manually using the PKTEND pin. In this scenario, the user must ensure to assert PKTEND at least one clock cycle after the rising edge that

caused the last byte or word to be clocked into the previous auto committed packet. Figure 23 shows this scenario. X is the value the AUTOINLEN register is set to when the IN endpoint is configured to be in auto mode.

Figure 23 shows a scenario where two packets are committed. The first packet gets committed automatically when the number of bytes in the FIFO reaches X (value set in AUTOINLEN register) and the second one byte/word short packet being committed manually using PKTEND.

Note that there is at least one IFCLK cycle timing between the assertion of PKTEND and clocking of the last byte of the previous packet (causing the packet to be committed automatically). Failing to adhere to this timing results in the FX2 failing to send the one byte or word short packet.

Figure 23. Slave FIFO Synchronous Write Sequence and Timing Diagram[20]

 

 

tIFCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IFCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSFA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tFAH

 

FIFOADR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

>= tSWR

 

 

 

 

 

 

 

 

 

 

 

 

>= tWRH

 

 

SLWR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

tFDH

tSFD

t

t

SFD

tFDH

t

t

FDH

t

t

t

t

 

 

SFD

 

 

FDH

 

 

SFD

 

SFD

FDH

SFD

FDH

 

 

DATA

X-4

 

X-3

 

 

X-2

 

X-1

 

 

X

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

At least one IFCLK cycle

tSPE

tPEH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PKTEND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10.12 Slave FIFO Asynchronous Packet End Strobe

Figure 24. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[20]

PKTEND

tPEpwl

tPEpwh

FLAGS

tXFLG

Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters[23]

Parameter

Description

Min

Max

Unit

tPEpwl

PKTEND Pulse Width LOW

50

 

ns

tPWpwh

PKTEND Pulse Width HIGH

50

 

ns

tXFLG

PKTEND to FLAGS Output Propagation Delay

 

115

ns

Document #: 38-08032 Rev. *L

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Cypress CY7C68013A Slave Fifo Asynchronous Packet End Strobe, Slave Fifo Synchronous Write Sequence and Timing Diagram

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.