128 | Cypress CY7C68013A manual

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 6. Signal

Port

GPIF Master

Slave FIFO

PD7

FD[15]

FD[15]

PD6

FD[14]

FD[14]

PD5

FD[13]

FD[13]

PD4

FD[12]

FD[12]

PD3

FD[11]

FD[11]

PD2

FD[10]

FD[10]

PD1

FD[9]

FD[9]

PD0

FD[8]

FD[8]

PB7

FD[7]

FD[7]

PB6

FD[6]

FD[6]

XTALIN

PB5

FD[5]

FD[5]

PB4

FD[4]

FD[4]

XTALOUT

PB3

FD[3]

FD[3]

RESET#

PB2

FD[2]

FD[2]

WAKEUP#

PB1

FD[1]

FD[1]

SCL

56

PB0

FD[0]

FD[0]

SDA

RDY0

SLRD

**PE0 replaces IFCLK

RDY1

SLWR

& PE1 replaces CLKOUT

CTL0

FLAGA

on CY7C68015A/16A

CTL1

FLAGB

**PE0

CTL2

FLAGC

**PE1

INT0#/PA0

INT0#/PA0

INT0#/ PA0

IFCLK

INT1#/PA1

INT1#/PA1

INT1#/ PA1

CLKOUT

PA2

PA2

SLOE

WU2/PA3

WU2/PA3

WU2/PA3

DPLUS

PA4

PA4

FIFOADR0

DMINUS

PA5

PA5

FIFOADR1

PA6

PA6

PKTEND

PA7

PA7

PA7/FLAGD/SLCS#

CTL3

CTL4

CTL5

RDY2

RDY3

100

RDY4

RDY5

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

RxD0

PORTC3/GPIFADR3

TxD0

PORTC2/GPIFADR2

RxD1

PORTC1/GPIFADR1

TxD1

PORTC0/GPIFADR0

INT4

PE7/GPIFADR8

INT5#

T2

PE6/T2EX

T1

PE5/INT6

PE4/RxD1OUT

T0

PE3/RxD0OUT

PE2/T2OUT

RD#

PE1/T1OUT

PE0/T0OUT

WR#

D7

CS#

D6

OE#

D5

PSEN#

D4

D3

A15

D2

A14

D1

A13

D0

A12

A11

128

A10

A9

A8

A7

A6

A5

EA

A4

A3

A2

A1

A0

Document #: 38-08032 Rev. *L

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Cypress CY7C68013A manual 128

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.

Contents

Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A/15A/16A Logic Block Diagram Features CY7C68013A/14A onlyFeatures CY7C68015A/16A only Functional Overview Applications Interrupt System USB Boot MethodsBus-powered Applications ReNumeration INT2 USB Interrupts Priority INT2VEC Value SourceFIFO/GPIF Interrupt INT4 Reset Pin Reset and Wakeup Program/Data RAM Reset Timing Values Condition Internal Code Memory, EA = Inside FX2LP Outside FX2LP External Code Memory, EA = Register Addresses Size × 64 bytes Endpoints 0 × 512 bytes Setup Data BufferEndpoint Configurations High -speed Mode Endpoint RAM Architecture 12.5 Default Full-Speed Alternate SettingsMaster/Slave Control Signals External Fifo Interface USB Uploads and Downloads Autopointer AccessECC Generation7 Gpif Package Description 18 I2C ControllerCompatible with Previous Generation EZ-USB FX2 Part Number Conversion Table PE1 Pin Assignments20 CY7C68013A/14A and CY7C68015A/16A Differences Ifclk PE0 128 Pin Tqfp CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68013A/CY7C68014A 56-pin Ssop CY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 128 100 56 VF Name Type Default 56 VF Name Type Default Description FX2LP Pin DescriptionsPort FIFOADR1 IFCONFIG1..0WU2 FIFOADR0 PORTCCFG.1 GPIFADR0PORTCCFG.0 GPIFADR1 T2OUT Port ET0OUT T1OUT GPIFADR8 RXD1OUTINT6 T2EX CTL4 FlagbFlagc CTL3 Ground FX2LP Register Summary Register Summary Register can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit ΘJc + θCa Thermal CharacteristicsAbsolute Maximum Ratings Operating Conditions DC Characteristics AC Electrical CharacteristicsUSB Transceiver Program Memory Read ClkoutProgram Memory Read Parameters Description Min Typ Max Unit Data Memory Read CLKOUT17Data Memory Read Parameters Description Min Typ Max Unit Data Memory Write Stretch =Data Memory Write Parameters Description Min Max Unit WR# Strobe Function when Portc is Accessed by Portc Strobe Feature Timings Gpif Synchronous Signals Timing Diagram20 Gpif Synchronous Signals Slave Fifo Synchronous Read Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Asynchronous Read Slave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Synchronous Write Slave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous Packet End Strobe Slave Fifo Asynchronous Write Slave Fifo Asynchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Address to Flags/Data Slave Fifo Output Enable RD/WR/PKTEND to FIFOADR10 Hold Time FIFOADR10 to SLRD/SLWR/PKTEND Setup TimeSlave Fifo Synchronous Address Slave Fifo Asynchronous Address Single and Burst Synchronous Read Example Sequence Diagram 10.17.2 Single and Burst Synchronous Write Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Write Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Write Development Tool Kit Ideal for battery powered applicationsIdeal for non-battery powered applications Ordering Information Lead Shrunk Small Outline Package O56 Package Diagrams Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout Recommendations Cross-section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design Notes Issue Orig. Description of Change Date Pyrs Cmcc