Cypress CY7C68013A manual Program Memory Read, Clkout

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.2 Program Memory Read
	Figure 12. Program Memory Read Timing Diagram
tCL
CLKOUT[17]
tAV		tAV
A[15..0]
	tSTBL	tSTBH
PSEN#
D[7..0]	[18]	tDH
	tACC1	data in
tSOEL
OE#
tSCSL
CS#

Table 15. Program Memory Read Parameters

Parameter	Description	Min	Typ	Max	Unit	Notes
tCL	1/CLKOUT Frequency		20.83		ns	48 MHz
			41.66		ns	24 MHz
			83.2		ns	12 MHz
tAV	Delay from Clock to Valid Address	0		10.7	ns
tSTBL	Clock to PSEN Low	0		8	ns
tSTBH	Clock to PSEN High	0		8	ns
tSOEL	Clock to OE Low			11.1	ns
tSCSL	Clock to CS Low			13	ns
tDSU	Data Setup to Clock	9.6			ns
tDH	Data Hold Time	0			ns

Notes

17.CLKOUT is shown with positive polarity.

18.tACC1 is computed from the above parameters as follows: tACC1(24 MHz) = 3*tCL – tAV – tDSU = 106 ns

tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.

Document #: 38-08032 Rev. *L Page 38 of 62

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