CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E6CB

1

FLOWSTB

Flowstate Strobe

SLAVE

RDYASYNC

CTLTOGL

SUSTAIN

0

MSTB2

MSTB1

MSTB0

00100000

RW

 

 

 

Configuration

 

 

 

 

 

 

 

 

 

 

E6CC

1

FLOWSTBEDGE

Flowstate Rising/Falling

0

0

0

0

0

0

FALLING

RISING

00000001

rrrrrrbb

 

 

 

Edge Configuration

 

 

 

 

 

 

 

 

 

 

E6CD

1

FLOWSTBPERIOD

Master-Strobe Half-Period

D7

D6

D5

D4

D3

D2

D1

D0

00000010

RW

E6CE

1

GPIFTCB3[11]

GPIF Transaction Count

TC31

TC30

TC29

TC28

TC27

TC26

TC25

TC24

00000000

RW

 

 

 

Byte 3

 

 

 

 

 

 

 

 

 

 

E6CF

1

GPIFTCB2[11]

GPIF Transaction Count

TC23

TC22

TC21

TC20

TC19

TC18

TC17

TC16

00000000

RW

 

 

 

Byte 2

 

 

 

 

 

 

 

 

 

 

E6D0

1

GPIFTCB1[11]

GPIF Transaction Count

TC15

TC14

TC13

TC12

TC11

TC10

TC9

TC8

00000000

RW

 

 

 

Byte 1

 

 

 

 

 

 

 

 

 

 

E6D1

1

GPIFTCB0[11]

GPIF Transaction Count

TC7

TC6

TC5

TC4

TC3

TC2

TC1

TC0

00000001

RW

 

 

 

Byte 0

 

 

 

 

 

 

 

 

 

 

 

2

reserved

 

 

 

 

 

 

 

 

 

00000000

RW

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

E6D2

1

EP2GPIFFLGSEL[11]

Endpoint 2 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6D3

1

EP2GPIFPFSTOP

Endpoint 2 GPIF stop

0

0

0

0

0

0

0

FIFO2FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6D4

1

EP2GPIFTRIG[11]

Endpoint 2 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

E6DA

1

EP4GPIFFLGSEL[11]

Endpoint 4 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6DB

1

EP4GPIFPFSTOP

Endpoint 4 GPIF stop

0

0

0

0

0

0

0

FIFO4FLAG

00000000

RW

 

 

 

transaction on GPIF Flag

 

 

 

 

 

 

 

 

 

 

E6DC

1

EP4GPIFTRIG[11]

Endpoint 4 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

E6E2

1

EP6GPIFFLGSEL[11]

Endpoint 6 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6E3

1

EP6GPIFPFSTOP

Endpoint 6 GPIF stop

0

0

0

0

0

0

0

FIFO6FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6E4

1

EP6GPIFTRIG[11]

Endpoint 6 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

E6EA

1

EP8GPIFFLGSEL[11]

Endpoint 8 GPIF Flag

0

0

0

0

0

0

FS1

FS0

00000000

RW

 

 

 

select

 

 

 

 

 

 

 

 

 

 

E6EB

1

EP8GPIFPFSTOP

Endpoint 8 GPIF stop

0

0

0

0

0

0

0

FIFO8FLAG

00000000

RW

 

 

 

transaction on prog. flag

 

 

 

 

 

 

 

 

 

 

E6EC

1

EP8GPIFTRIG[11]

Endpoint 8 GPIF Trigger

x

x

x

x

x

x

x

x

xxxxxxxx

W

 

3

reserved

 

 

 

 

 

 

 

 

 

 

 

E6F0

1

XGPIFSGLDATH

GPIF Data H

D15

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx

RW

 

 

 

(16-bit mode only)

 

 

 

 

 

 

 

 

 

 

E6F1

1

XGPIFSGLDATLX

Read/Write GPIF Data L &

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

trigger transaction

 

 

 

 

 

 

 

 

 

 

E6F2

1

XGPIFSGLDATL-

Read GPIF Data L, no

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

R

 

 

NOX

transaction trigger

 

 

 

 

 

 

 

 

 

 

E6F3

1

GPIFREADYCFG

Internal RDY, Sync/Async,

INTRDY

SAS

TCXRDY5

0

0

0

0

0

00000000

bbbrrrrr

 

 

 

RDY pin states

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E6F4

1

GPIFREADYSTAT

GPIF Ready Status

0

0

RDY5

RDY4

RDY3

RDY2

RDY1

RDY0

00xxxxxx

R

E6F5

1

GPIFABORT

Abort GPIF Waveforms

x

x

x

x

x

x

x

x

xxxxxxxx

W

E6F6

2

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

ENDPOINT BUFFERS

 

 

 

 

 

 

 

 

 

 

 

E740

64

EP0BUF

EP0-IN/-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E780

64

EP10UTBUF

EP1-OUT buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E7C0

64

EP1INBUF

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

E800

2048

reserved

 

 

 

 

 

 

 

 

 

 

RW

F000

1024

EP2FIFOBUF

512/1024 byte EP 2 / slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

FIFO buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

F400

512

EP4FIFOBUF

512 byte EP 4 / slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

F600

512

reserved

 

 

 

 

 

 

 

 

 

 

 

F800

1024

EP6FIFOBUF

512/1024 byte EP 6 / slave

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

FIFO buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

FC00

512

EP8FIFOBUF

512 byte EP 8 / slave FIFO

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx

RW

 

 

 

buffer (IN or OUT)

 

 

 

 

 

 

 

 

 

 

FE00

512

reserved

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-08032 Rev. *L

Page 33 of 62

[+] Feedback

Page 33
Image 33
Cypress CY7C68013A manual E6CB Flowstb

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.