Cypress CY7C68013A - page 28

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Document #: 38-08032 Rev. *L Page 28 of 62

50 40 TXD0 Output H TXD0 is the active-HIGH TXD0 output from 8051

UART0, which provides the output clock in sync mode,

and the output data in async mode.

42 CS# Output H CS# is the active-LOW chip select for external memory.

41 32 WR# Output H WR# is the active-LOW write strobe output for external

memory.

40 31 RD# Output H RD# is the active-LOW read strobe output for external

memory.

38 OE# Output H OE# is the active-LOW output enable for external

memory.

33 27 21 14 2H Reserved Input N/A Reserved. Connect to ground.

101 79 51 44 7B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this

pin starts up the oscillator and interrupts the 8051 to

enable it to exit the suspend mode. Holding WAKEUP

asserted inhibits the EZ-USB® chip from suspending.

This pin has programmable polarity (WAKEUP.4).

36 29 22 15 3F SCL OD Z Clock for the I2C interfac e. Connect to VCC with a 2.2K

resistor, even if no I2C peripheral is attached.

37 30 23 16 3G SDA OD Z Data for I2C-compatible interface. Connect to VCC

with a 2.2K resistor, even if no I2C-compatible

peripheral is attached.

216555AVCC PowerN/AVCC. Connect to 3.3V power source.

26 20 18 11 1G VCC Power N/A VCC. Connect to 3.3V power source.

43 33 24 17 7E VCC Power N/A VCC. Connect to 3.3V power source.

48 38 VCC Power N/A VCC. Connect to 3.3V power source.

64 49 34 27 8E VCC Power N/A VCC. Connect to 3.3V power source.

68 53 VCC Power N/A VCC. Connect to 3.3V power source.

81 66 39 32 5C VCC Power N/A VCC. Connect to 3.3V power source.

100 78 50 43 5B VCC Power N/A VCC. Connect to 3.3V power source.

107 85 VCC Power N/A VCC. Connect to 3.3V power source.

3 2 7 56 4B GND Ground N/A Ground.

27 21 19 12 1H GND Ground N/A Ground.

49 39 GND Ground N/A Ground.

58 48 33 26 7D GND Ground N/A Ground.

65 50 35 28 8D GND Ground N/A Ground.

80 65 GND Ground N/A Ground.

93 75 48 41 4C GND Ground N/A Ground.

116 94 GND Ground N/A Ground.

125 99 4 53 4A GND Ground N/A Ground.

14 13 NC N/A N/A No Connect. This pin must be left open.

15 14 NC N/A N/A No Connect. This pin must be left open.

16 15 NC N/A N/A No Connect. This pin must be left open.

Table 11. FX2LP Pin Descriptions (continued)

128

TQFP 100

TQFP 56

SSOP 56

QFN 56 VF-

BGA Name Type Default Description

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Contents

Main CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller 1. Features (CY7C68013A/14A/15A/16A) 1.1 Features (CY7C68013A/14A only) 1.2 Features (CY7C68015A/16A only) FX2LP Logic Block DiagramLogic Block Diagram CY7C68013A, CY7C68014A 2. Applications 3. Functional Overview 3.1 USB Signaling Speed 3.2 8051 Microprocessor CY7C68013A, CY7C68014A 3.5 USB Boot Methods 3.6 ReNumeration 3.7 Bus-powered Applications 3.8 Interrupt System CY7C68015A, CY7C68016A CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.9 Reset and Wakeup CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A 3.10 Program/Data RAM CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A Document #: 38-08032 Rev. *L Page 8 of 62 *SUDPTR, USB upload/download, I2C interface boot access Figure 3. Internal Code Memory, EA = 0 Inside FX2LP Outside FX2LP 3.11 Register Addresses *SUDPTR, USB upload/download, I2C interface boot access Inside FX2LP Outside FX2LP E73F 3.12 Endpoint RAM 3.13 External FIFO Interface 3.14 GPIF 3.15 ECC Generation 3.16 USB Uploads and Downloads 3.17 Autopointer Access CY7C68013A, CY7C68014A 3.18 I2C Controller 3.19 Compatible with Previous Generation EZ-USB FX2 CY7C68013A, CY7C68014A 3.20 CY7C68013A/14A and CY7C68015A/16A Differences 4. Pin Assignments CY7C68015A, CY7C68016A Figure 6. Signal Port GPIF Master Slave FIFO CY7C68015A, CY7C68016A 128-pin TQFP * denotes programmable polarity 100-pin TQFP 56-pin SSOP & CY7C68015A/CY7C68016A 56-pin QFN Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View 4.1 CY7C68013A/15A Pin Descriptions Page Page Page Page Page Page Page 5. Register Summary 12.The register can only be reset, it cannot be set. Page Document #: 38-08032 Rev. *L Page 32 of 62 Page Page r = read-only bit w = write-only bit b = both read/write bit R = all bits read-only W = all bits write-only 6. Absolute Maximum Ratings 7. Operating Conditions 8. Thermal Characteristics Ja = Junction to Ambient Temperature ( Jc + 9. DC Characteristics 9.1 USB Transceiver 10. AC Electrical Characteristics 10.1 USB Transceiver 10.2 Program Memory Read 10.3 Data Memory Read 10.4 Data Memory Write 10.5 PORTC Strobe Feature Timings 10.6 GPIF Synchronous Signals 10.7 Slave FIFO Synchronous Read 10.8 Slave FIFO Asynchronous Read 10.9 Slave FIFO Synchronous Write 10.10 Slave FIFO Asynchronous Write 10.11 Slave FIFO Synchronous Packet End Strobe 10.12 Slave FIFO Asynchronous Packet End Strobe 10.13 Slave FIFO Output Enable 10.14 Slave FIFO Address to Flags/Data 10.15 Slave FIFO Synchronous Address 10.16 Slave FIFO Asynchronous Address 10.17 Sequence Diagram Page Page Page 11. Ordering Information 12. Package Diagrams Package Diagrams 51-85144-*D Figure 36. 56-Lead QFN 8 x 8 mm LF56A (51-85144) TOP VIEW BOTTOM VIEW SIDE VIEW NOTES: A Figure 37. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A100RA (51-85050) A Figure 38. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 (51-85101) 13. PCB Layout Recommendations 14. Quad Flat Package No Leads (QFN) Package Design Notes PCB Material PCB Material Document History Page