Ground | Cypress CY7C68013A specs

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128

100

56

56

56 VF-

Name

Type

Default

Description

TQFP

TQFP

SSOP

QFN

BGA

50

40

TXD0

Output

H

TXD0 is the active-HIGH TXD0 output from 8051

UART0, which provides the output clock in sync mode,

and the output data in async mode.

42

CS#

Output

H

CS# is the active-LOW chip select for external memory.

41

32

WR#

Output

H

WR# is the active-LOW write strobe output for external

memory.

40

31

RD#

Output

H

RD# is the active-LOW read strobe output for external

memory.

38

OE#

Output

H

OE# is the active-LOW output enable for external

memory.

33

27

21

14

2H

Reserved

Input

N/A

Reserved. Connect to ground.

101

79

51

44

7B

WAKEUP

Input

N/A

USB Wakeup. If the 8051 is in suspend, asserting this

pin starts up the oscillator and interrupts the 8051 to

enable it to exit the suspend mode. Holding WAKEUP

asserted inhibits the EZ-USB→chip from suspending.

This pin has programmable polarity (WAKEUP.4).

36

29

22

15

3F

SCL

OD

Z

Clock for the I2C interface. Connect to VCC with a 2.2K

resistor, even if no I2C peripheral is attached.

37

30

23

16

3G

SDA

OD

Z

Data for I2C-compatible interface. Connect to VCC

with a 2.2K resistor, even if no I2C-compatible

peripheral is attached.

2

1

6

55

5A

VCC

Power

N/A

VCC. Connect to 3.3V power source.

26

20

18

11

1G

VCC

Power

N/A

VCC. Connect to 3.3V power source.

43

33

24

17

7E

VCC

Power

N/A

VCC. Connect to 3.3V power source.

48

38

VCC

Power

N/A

VCC. Connect to 3.3V power source.

64

49

34

27

8E

VCC

Power

N/A

VCC. Connect to 3.3V power source.

68

53

VCC

Power

N/A

VCC. Connect to 3.3V power source.

81

66

39

32

5C

VCC

Power

N/A

VCC. Connect to 3.3V power source.

100

78

50

43

5B

VCC

Power

N/A

VCC. Connect to 3.3V power source.

107

85

VCC

Power

N/A

VCC. Connect to 3.3V power source.

3

2

7

56

4B

GND

Ground

N/A

Ground.

27

21

19

12

1H

GND

Ground

N/A

Ground.

49

39

GND

Ground

N/A

Ground.

58

48

33

26

7D

GND

Ground

N/A

Ground.

65

50

35

28

8D

GND

Ground

N/A

Ground.

80

65

GND

Ground

N/A

Ground.

93

75

48

41

4C

GND

Ground

N/A

Ground.

116

94

GND

Ground

N/A

Ground.

125

99

4

53

4A

GND

Ground

N/A

Ground.

14

13

NC

N/A

N/A

No Connect. This pin must be left open.

15

14

NC

N/A

N/A

No Connect. This pin must be left open.

16

15

NC

N/A

N/A

No Connect. This pin must be left open.

Document #: 38-08032 Rev. *L

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Cypress CY7C68013A manual Ground

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.

Contents

Features CY7C68013A/14A/15A/16A Cypress Semiconductor Corporation 198 Champion Court Features CY7C68013A/14A only Logic Block DiagramFeatures CY7C68015A/16A only Applications Functional Overview USB Boot Methods Bus-powered ApplicationsReNumeration Interrupt System Priority INT2VEC Value Source INT2 USB InterruptsFIFO/GPIF Interrupt INT4 Reset and Wakeup Reset Pin Reset Timing Values Condition Program/Data RAM Inside FX2LP Outside FX2LP Internal Code Memory, EA = Register Addresses External Code Memory, EA = Setup Data Buffer Endpoint Configurations High -speed ModeEndpoint RAM Size × 64 bytes Endpoints 0 × 512 bytes 12.5 Default Full-Speed Alternate Settings Master/Slave Control SignalsExternal Fifo Interface Architecture Autopointer Access ECC Generation7Gpif USB Uploads and Downloads 18 I2C Controller Compatible with Previous Generation EZ-USB FX2Part Number Conversion Table Package Description Pin Assignments 20 CY7C68013A/14A and CY7C68015A/16A DifferencesIfclk PE0 PE1 128 CY7C68013A/CY7C68014A Pin Tqfp CY7C68013A/CY7C68014A CY7C68013A/CY7C68014A 56-pin Ssop CY7C68013A/CY7C68014A 56-pin Ssop Pin Assignment CY7C68015A/CY7C68016A Pin QFN CY7C68013A 56-pin Vfbga Pin Assignment Top View FX2LP Pin Descriptions 128 100 56 VF Name Type Default CY7C68013A/15A Pin Descriptions FX2LP Pin Descriptions 56 VF Name Type Default DescriptionPort IFCONFIG1..0 WU2FIFOADR0 FIFOADR1 GPIFADR0 PORTCCFG.0GPIFADR1 PORTCCFG.1 Port E T0OUTT1OUT T2OUT RXD1OUT INT6T2EX GPIFADR8 Flagb FlagcCTL3 CTL4 Ground Register Summary FX2LP Register Summary Register can only be reset, it cannot be set Epie EP0CS E6CB Flowstb DPL0 = both read/write bit Thermal Characteristics Absolute Maximum RatingsOperating Conditions ΘJc + θCa AC Electrical Characteristics DC CharacteristicsUSB Transceiver Clkout Program Memory ReadProgram Memory Read Parameters Description Min Typ Max Unit CLKOUT17 Data Memory ReadData Memory Read Parameters Description Min Typ Max Unit Stretch = Data Memory WriteData Memory Write Parameters Description Min Max Unit Portc Strobe Feature Timings WR# Strobe Function when Portc is Accessed by Gpif Synchronous Signals Gpif Synchronous Signals Timing Diagram20 Slave Fifo Synchronous Read Timing Diagram20 Slave Fifo Synchronous Read Slave Fifo Asynchronous Read Timing Diagram20 Slave Fifo Asynchronous Read Slave Fifo Synchronous Write Timing Diagram20 Slave Fifo Synchronous Write Slave Fifo Asynchronous Write Slave Fifo Synchronous Packet End Strobe Slave Fifo Synchronous Write Sequence and Timing Diagram Slave Fifo Asynchronous Packet End Strobe Slave Fifo Output Enable Slave Fifo Address to Flags/Data FIFOADR10 to SLRD/SLWR/PKTEND Setup Time Slave Fifo Synchronous AddressSlave Fifo Asynchronous Address RD/WR/PKTEND to FIFOADR10 Hold Time Sequence Diagram Single and Burst Synchronous Read Example 10.17.2 Single and Burst Synchronous Write Sequence Diagram of a Single and Burst Asynchronous Read Slave Fifo Asynchronous Read Sequence and Timing Diagram20 Sequence Diagram of a Single and Burst Asynchronous Write Slave Fifo Asynchronous Write Sequence and Timing Diagram20 Ideal for battery powered applications Ideal for non-battery powered applicationsOrdering Information Development Tool Kit Package Diagrams Lead Shrunk Small Outline Package O56 Lead QFN 8 x 8 mm LF56A Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A100RA Lead Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm A128 PCB Layout Recommendations Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 Quad Flat Package No Leads QFN Package Design Notes Cross-section of the Area Underneath the QFN Package Issue Orig. Description of Change Date Cmcc Pyrs