CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex

Size

Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E62B

1

ECC1B1

ECC1 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62C

1

ECC1B2

ECC1 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

LINE17

LINE16

00000000

R

E62D

1

ECC2B0

ECC2 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000

R

E62E

1

ECC2B1

ECC2 Byte 1 Address

LINE7

LINE6

LINE5

LINE4

LINE3

LINE2

LINE1

LINE0

00000000

R

E62F

1

ECC2B2

ECC2 Byte 2 Address

COL5

COL4

COL3

COL2

COL1

COL0

0

0

00000000

R

E630

1

EP2FIFOPFH[11]

Endpoint 2 / slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

10001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E630

1

EP2FIFOPFH[11]

Endpoint 2 / slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

10001000

bbbbbrbb

F.S.

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E631

1

EP2FIFOPFL[11]

Endpoint 2 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E631

1

EP2FIFOPFL[11]

Endpoint 2 / slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E632

1

EP4FIFOPFH[11]

Endpoint 4 / slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

10001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E632

1

EP4FIFOPFH[11]

Endpoint 4 / slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

10001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[11]

Endpoint 4 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E633

1

EP4FIFOPFL[11]

Endpoint 4 / slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E634

1

EP6FIFOPFH[11]

Endpoint 6 / slave FIFO

DECIS

PKTSTAT

IN:PKTS[2]

IN:PKTS[1]

IN:PKTS[0]

0

PFC9

PFC8

00001000

bbbbbrbb

H.S.

 

 

Programmable Flag H

 

 

OUT:PFC12

OUT:PFC11

OUT:PFC10

 

 

 

 

 

E634

1

EP6FIFOPFH[11]

Endpoint 6 / slave FIFO

DECIS

PKTSTAT

OUT:PFC12

OUT:PFC11

OUT:PFC10

0

PFC9

IN:PKTS[2]

00001000

bbbbbrbb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

OUT:PFC8

 

 

E635

1

EP6FIFOPFL[11]

Endpoint 6 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E635

1

EP6FIFOPFL[11]

Endpoint 6 / slave FIFO

IN:PKTS[1]

IN:PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

E636

1

EP8FIFOPFH[11]

Endpoint 8 / slave FIFO

DECIS

PKTSTAT

0

IN: PKTS[1]

IN: PKTS[0]

0

0

PFC8

00001000

bbrbbrrb

H.S.

 

 

Programmable Flag H

 

 

 

OUT:PFC10

OUT:PFC9

 

 

 

 

 

E636

1

EP8FIFOPFH[11]

Endpoint 8 / slave FIFO

DECIS

PKTSTAT

0

OUT:PFC10

OUT:PFC9

0

0

PFC8

00001000

bbrbbrrb

F.S

 

 

Programmable Flag H

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[11]

Endpoint 8 / slave FIFO

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

H.S.

 

 

Programmable Flag L

 

 

 

 

 

 

 

 

 

 

E637

1

EP8FIFOPFL[11]

Endpoint 8 / slave FIFO

IN: PKTS[1]

IN: PKTS[0]

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000

RW

F.S

 

 

Programmable Flag L

OUT:PFC7

OUT:PFC6

 

 

 

 

 

 

 

 

 

8

reserved

 

 

 

 

 

 

 

 

 

 

 

E640

1

EP2ISOINPKTS

EP2 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E641

1

EP4ISOINPKTS

EP4 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E642

1

EP6ISOINPKTS

EP6 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrbb

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E643

1

EP8ISOINPKTS

EP8 (if ISO) IN Packets

AADJ

0

0

0

0

0

INPPF1

INPPF0

00000001

brrrrrrr

 

 

 

per frame (1-3)

 

 

 

 

 

 

 

 

 

 

E644

4

reserved

 

 

 

 

 

 

 

 

 

 

 

E648

1

INPKTEND[11]

Force IN Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

E649

7

OUTPKTEND[11]

Force OUT Packet End

Skip

0

0

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

 

 

INTERRUPTS

 

 

 

 

 

 

 

 

 

 

 

E650

1

EP2FIFOIE[11]

Endpoint 2 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E651

1

EP2FIFOIRQ[11,12]

Endpoint 2 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E652

1

EP4FIFOIE[11]

Endpoint 4 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E653

1

EP4FIFOIRQ[11,12]

Endpoint 4 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E654

1

EP6FIFOIE[11]

Endpoint 6 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E655

1

EP6FIFOIRQ[11,12]

Endpoint 6 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E656

1

EP8FIFOIE[11]

Endpoint 8 slave FIFO

0

0

0

0

EDGEPF

PF

EF

FF

00000000

RW

 

 

 

Flag Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E657

1

EP8FIFOIRQ[11,12]

Endpoint 8 slave FIFO

0

0

0

0

0

PF

EF

FF

00000000

rrrrrbbb

 

 

 

Flag Interrupt Request

 

 

 

 

 

 

 

 

 

 

E658

1

IBNIE

IN-BULK-NAK Interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00000000

RW

 

 

 

Enable

 

 

 

 

 

 

 

 

 

 

E659

1

IBNIRQ[12]

IN-BULK-NAK interrupt

0

0

EP8

EP6

EP4

EP2

EP1

EP0

00xxxxxx

rrbbbbbb

 

 

 

Request

 

 

 

 

 

 

 

 

 

 

E65A

1

NAKIE

Endpoint Ping-NAK / IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

00000000

RW

 

 

 

Interrupt Enable

 

 

 

 

 

 

 

 

 

 

E65B

1

NAKIRQ[12]

Endpoint Ping-NAK / IBN

EP8

EP6

EP4

EP2

EP1

EP0

0

IBN

xxxxxx0x

bbbbbbrb

 

 

 

Interrupt Request

 

 

 

 

 

 

 

 

 

 

E65C

1

USBIE

USB Int Enables

0

EP0ACK

HSGRANT

URES

SUSP

SUTOK

SOF

SUDAV

00000000

RW

Note

12. The register can only be reset, it cannot be set.

Document #: 38-08032 Rev. *L

Page 30 of 62

[+] Feedback

Page 30
Image 30
Cypress CY7C68013A manual Register can only be reset, it cannot be set

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.