Cypress CY7C68013A manual Sequence Diagram of a Single and Burst Asynchronous Write

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram[20]

tSFA

tFAH

tSFA

tFAH

FIFOADR

t=0

tWRpwl

tWRpwh

T=0

tWRpwl

tWRpwh

tWRpwl

tWRpwh

tWRpwl

tWRpwh

SLWR

t =1

t=3

T=1

T=3

T=4

T=6

T=7

T=9

SLCS

tXFLG

tXFLG

FLAGS

tSFD

tFDH

t

t

FDH

t

t

t

t

FDH

SFD

SFD

FDH

SFD

DATA

N

N+1

N+2

N+3

t=2

T=2

T=5

T=8

tPEpwl

tPEpwh

PKTEND

Figure 34 shows the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single write followed by a burst write of 3 bytes and committing the 4 byte short packet using PKTEND.

■At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS may be tied low in some applications).

■At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh. If the SLCS is used, it must be asserted with SLWR or before SLWR is asserted.

■At t = 2, data must be present on the bus tSFD before the deasserting edge of SLWR.

■At t = 3, deasserting SLWR causes the data to be written from the data bus to the FIFO and then increments the FIFO pointer.

The FIFO flag is also updated after tXFLG from the deasserting edge of SLWR.

The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5.

Note In the burst write mode, after SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next byte in the FIFO. The FIFO pointer is post incre- mented.

In Figure 34 after the four bytes are written to the FIFO and SLWR is deasserted, the short 4 byte packet can be committed to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines have to held constant during the PKTEND assertion.

Document #: 38-08032 Rev. *L Page 53 of 62

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