CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 42 of 62
10.6 GPIF Synchronous Signals
Figure 17. GPIF Synchronous Signals Timing Diagram[20]
DATA(output)
tXGD
IFCLK
RDYX
DATA(input) valid
tSRY
tRYH
tIFCLK
tSGD
CTL
X
t
XCTL
tDAH
NN+1
GPIFADR[8:0]
tSGA
Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[20, 21]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSRY RDYX to Clock Setup Time 8.9 ns
tRYH Clock to RDYX 0ns
tSGD GPIF Data to Clock Setup Time 9.2 ns
tDAH GPIF Data Hold Time 0 ns
tSGA Clock to GPIF Address Propagation Delay 7.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 11 ns
tXCTL Clock to CTLX Output Propagation Delay 6.7 ns
Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[21]
Parameter Description Min. Max. Unit
tIFCLK IFCLK Period[22] 20.83 200 ns
tSRY RDYX to Clock Setup Time 2.9 ns
tRYH Clock to RDYX 3.7 ns
tSGD GPIF Data to Clock Setup Time 3.2 ns
tDAH GPIF Data Hold Time 4.5 ns
tSGA Clock to GPIF Address Propagation Delay 11.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 15 ns
tXCTL Clock to CTLX Output Propagation Delay 10.7 ns
Notes
20.Dashed lines denote signals with programmable polarity.
21.GPIF asynchronous RDYx signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
22.IFCLK must not exceed 48 MHz.
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