Contents
Main
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
EZ-USB FX2LP USB Microcontroller High-Speed USB Peripheral Controller
1. Features (CY7C68013A/14A/15A/16A)
1.1 Features (CY7C68013A/14A only)
1.2 Features (CY7C68015A/16A only)
FX2LP
Logic Block DiagramLogic Block Diagram
CY7C68013A, CY7C68014A
2. Applications
3. Functional Overview
3.1 USB Signaling Speed
3.2 8051 Microprocessor
CY7C68013A, CY7C68014A
3.5 USB Boot Methods
3.6 ReNumeration
3.7 Bus-powered Applications
3.8 Interrupt System
CY7C68015A, CY7C68016A
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
3.9 Reset and Wakeup
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
3.10 Program/Data RAM
CY7C68013A, CY7C68014A CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 8 of 62
*SUDPTR, USB upload/download, I2C interface boot access
Figure 3. Internal Code Memory, EA = 0
Inside FX2LP Outside FX2LP
3.11 Register Addresses
*SUDPTR, USB upload/download, I2C interface boot access
Inside FX2LP Outside FX2LP
E73F
3.12 Endpoint RAM
3.13 External FIFO Interface
3.14 GPIF
3.15 ECC Generation
3.16 USB Uploads and Downloads
3.17 Autopointer Access
CY7C68013A, CY7C68014A
3.18 I2C Controller
3.19 Compatible with Previous Generation EZ-USB FX2
CY7C68013A, CY7C68014A
3.20 CY7C68013A/14A and CY7C68015A/16A Differences
4. Pin Assignments
CY7C68015A, CY7C68016A
Figure 6. Signal
Port GPIF Master Slave FIFO
CY7C68015A, CY7C68016A
128-pin TQFP
* denotes programmable polarity
100-pin TQFP
56-pin SSOP
& CY7C68015A/CY7C68016A 56-pin QFN
Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View
4.1 CY7C68013A/15A Pin Descriptions
Page
Page
Page
Page
Page
Page
Page
5. Register Summary
12.The register can only be reset, it cannot be set.
Page
Document #: 38-08032 Rev. *L Page 32 of 62
Page
Page
r = read-only bit w = write-only bit b = both read/write bit
R = all bits read-only W = all bits write-only
6. Absolute Maximum Ratings
7. Operating Conditions
8. Thermal Characteristics
Ja = Junction to Ambient Temperature ( Jc +
9. DC Characteristics
9.1 USB Transceiver
10. AC Electrical Characteristics
10.1 USB Transceiver
10.2 Program Memory Read
10.3 Data Memory Read
10.4 Data Memory Write
10.5 PORTC Strobe Feature Timings
10.6 GPIF Synchronous Signals
10.7 Slave FIFO Synchronous Read
10.8 Slave FIFO Asynchronous Read
10.9 Slave FIFO Synchronous Write
10.10 Slave FIFO Asynchronous Write
10.11 Slave FIFO Synchronous Packet End Strobe
10.12 Slave FIFO Asynchronous Packet End Strobe
10.13 Slave FIFO Output Enable
10.14 Slave FIFO Address to Flags/Data
10.15 Slave FIFO Synchronous Address
10.16 Slave FIFO Asynchronous Address
10.17 Sequence Diagram
Page
Page
Page
11. Ordering Information
12. Package Diagrams
Package Diagrams
51-85144-*D
Figure 36. 56-Lead QFN 8 x 8 mm LF56A (51-85144)
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTES:
A
Figure 37. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A100RA (51-85050)
A
Figure 38. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 (51-85101)
13. PCB Layout Recommendations
14. Quad Flat Package No Leads (QFN) Package Design Notes
PCB Material PCB Material
Document History Page
