CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L Page 49 of 62
10.15 Slave FIFO Synchronous Address
Figure 27. Slave FIFO Synchronous Address Timing Diagram[20]
10.16 Slave FIFO Asynchronous Address
Figure 28. Slave FIFO Asynchronous Address Timing Diagram[20]
IFCLK
SLCS/FIFOADR [1:0]
tSFA tFAH
Table 31. Slave FIFO Synchronous Address Parameters [21]
Parameter Description Min Max Unit
tIFCLK Interface Clock Period 20.83 200 ns
tSFA FIFOADR[1:0] to Clock Setup Time 25 ns
tFAH Clock to FIFOADR[1:0] Hold Time 10 ns
Table 32. Slave FIFO Asynchronous Address Parameters[23]
Parameter Description Min Max Unit
tSFA FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time 10 ns
tFAH RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns
SLRD/SLWR/PKTEND
SLCS/FIFOADR [1:0]
tSFA tFAH
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