CY7C68013A, CY7C68014A

 

 

 

 

 

 

 

 

 

 

 

CY7C68015A, CY7C68016A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 11. FX2LP Pin Descriptions (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

128

 

100

56

56

56 VF-

Name

Type

Default

Description

 

 

TQFP

TQFP

SSOP

QFN

BGA

 

 

 

 

 

 

 

85

 

70

43

36

7F

PA3 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

WU2

 

(PA3)

WAKEUP.7 and OEA.3

 

 

 

 

 

 

 

 

 

 

 

 

PA3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

WU2 is an alternate source for USB Wakeup, enabled

 

 

 

 

 

 

 

 

 

 

 

 

by WU2EN bit (WAKEUP.1) and polarity set by

 

 

 

 

 

 

 

 

 

 

 

 

WU2POL (WAKEUP.4). If the 8051 is in suspend and

 

 

 

 

 

 

 

 

 

 

 

 

WU2EN = 1, a transition on this pin starts up the oscil-

 

 

 

 

 

 

 

 

 

 

 

 

lator and interrupts the 8051 to enable it to exit the

 

 

 

 

 

 

 

 

 

 

 

 

suspend mode. Asserting this pin inhibits the chip from

 

 

 

 

 

 

 

 

 

 

 

 

suspending, if WU2EN = 1.

 

89

 

71

44

37

6F

PA4 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

FIFOADR0

 

(PA4)

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PA4 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FIFOADR0 is an input-only address select for the slave

 

 

 

 

 

 

 

 

 

 

 

 

FIFOs connected to FD[7..0] or FD[15..0].

 

90

 

72

45

38

8C

PA5 or

IO/Z

I

Multiplexed pin whose function is selected by:

 

 

 

 

 

 

 

 

 

 

FIFOADR1

 

(PA5)

IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PA5 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FIFOADR1 is an input-only address select for the slave

 

 

 

 

 

 

 

 

 

 

 

 

FIFOs connected to FD[7..0] or FD[15..0].

 

91

 

73

46

39

7C

PA6 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

PKTEND

 

(PA6)

IFCONFIG[1:0] bits.

 

 

 

 

 

 

 

 

 

 

 

 

PA6 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

PKTEND is an input used to commit the FIFO packet

 

 

 

 

 

 

 

 

 

 

 

 

data to the endpoint and whose polarity is program-

 

 

 

 

 

 

 

 

 

 

 

 

mable via FIFOPINPOLAR.5.

 

92

 

74

47

40

6C

PA7 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FLAGD or

 

(PA7)

IFCONFIG[1:0] and PORTACFG.7 bits.

 

 

 

 

 

 

 

 

 

SLCS#

 

 

PA7 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FLAGD is a programmable slave-FIFO output status

 

 

 

 

 

 

 

 

 

 

 

 

flag signal.

 

 

 

 

 

 

 

 

 

 

 

 

SLCS# gates all other slave FIFO enable/strobes

 

Port

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44

 

34

25

18

3H

PB0 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[0]

 

(PB0)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB0 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[0] is the bidirectional FIFO/GPIF data bus.

 

45

 

35

26

19

4F

PB1 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[1]

 

(PB1)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB1 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[1] is the bidirectional FIFO/GPIF data bus.

 

46

 

36

27

20

4H

PB2 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[2]

 

(PB2)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB2 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[2] is the bidirectional FIFO/GPIF data bus.

 

47

 

37

28

21

4G

PB3 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[3]

 

(PB3)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB3 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[3] is the bidirectional FIFO/GPIF data bus.

 

54

 

44

29

22

5H

PB4 or

IO/Z

I

Multiplexed pin whose function is selected by the

 

 

 

 

 

 

 

 

 

 

FD[4]

 

(PB4)

following bits: IFCONFIG[1..0].

 

 

 

 

 

 

 

 

 

 

 

 

PB4 is a bidirectional IO port pin.

 

 

 

 

 

 

 

 

 

 

 

 

FD[4] is the bidirectional FIFO/GPIF data bus.

 

Document #: 38-08032 Rev. *L

 

 

 

Page 23 of 62

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Cypress CY7C68013A manual WU2, FIFOADR0, IFCONFIG1..0, FIFOADR1, Pktend, Slcs#

CY7C68013A specifications

The Cypress CY7C68013A is a high-performance USB microcontroller that belongs to Cypress's FX2LP family, specifically designed for USB applications. This microcontroller is well-regarded for its versatility, making it a popular choice for developers engaged in USB-enabled projects.

One of the main features of the CY7C68013A is its ability to support USB 2.0, with both high-speed (480 Mbps) and full-speed (12 Mbps) operation. This capability allows developers to take full advantage of the USB interface for data transfer, making it suitable for applications that require fast and efficient data communication. The device integrates a USB controller along with an 8051-compatible microcontroller, providing a seamless interface for USB transactions while also allowing for custom processing tasks.

The CY7C68013A offers 32 KB of internal RAM, which is a valuable resource for data buffering and temporary storage during data transfer operations. Additionally, it includes a programmable 8-bit I/O interface, which can be tailored to various application needs, facilitating control over peripheral devices. The microcontroller also features a 16-bit address bus and a 16-bit data bus, enhancing its ability to interface with external memory and components.

In terms of development, moving from concept to production becomes easier due to the availability of development kits and software support. The CY7C68013A is compatible with Cypress's EZ-USB development environment, which includes APIs and libraries that simplify the coding process. This software support empowers developers to create sophisticated USB-related applications without needing extensive background knowledge in USB protocol intricacies.

Regarding power efficiency, the CY7C68013A operates at low power consumption levels, making it suitable for battery-operated devices. It supports various low-power modes, which further enhances its appeal for portable applications.

Overall, the Cypress CY7C68013A stands out for its robust features, flexibility, and ease of use, making it an ideal choice for engineers working on USB-centric designs. Its combination of high-speed USB functionality, ample internal resources, and strong software support positions it as a go-to microcontroller for a wide variety of applications, ranging from consumer electronics to industrial systems.