Cypress CY7C68013A manual Data Memory Write, Stretch =

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

10.4 Data Memory Write

Figure 14. Data Memory Write Timing Diagram

tCL

CLKOUT
tAV	tSTBL	tSTBH	tAV
A[15..0]
WR#
	tSCSL
CS#
	tON1		tOFF1
D[7..0]		data out
tCL		Stretch = 1
CLKOUT
tAV

A[15..0]
WR#
CS#
		tON1						tOFF1
D[7..0]				data out
Table 17. Data Memory Write Parameters
Parameter			Description		Min	Max	Unit	Notes
tAV	Delay from Clock to Valid Address				0	10.7	ns
tSTBL	Clock to WR Pulse LOW				0	11.2	ns
tSTBH	Clock to WR Pulse HIGH				0	11.2	ns
tSCSL	Clock to CS Pulse LOW					13.0	ns
tON1	Clock to Data Turn-on				0	13.1	ns
tOFF1	Clock to Data Hold Time				0	13.1	ns

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is based on the stretch value.

Document #: 38-08032 Rev. *L Page 40 of 62

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