Cypress CY7C68013A GPIFADR0, PORTCCFG.0, GPIFADR1, PORTCCFG.1, GPIFADR2, PORTCCFG.2, GPIFADR3

								CY7C68013A, CY7C68014A
								CY7C68015A, CY7C68016A
Table 11. FX2LP Pin Descriptions (continued)
128	100	56	56	56 VF-	Name	Type	Default	Description
TQFP	TQFP	SSOP	QFN	BGA
55	45	30	23	5G	PB5 or	IO/Z	I	Multiplexed pin whose function is selected by the
					FD[5]		(PB5)	following bits: IFCONFIG[1..0].
								PB5 is a bidirectional IO port pin.
								FD[5] is the bidirectional FIFO/GPIF data bus.
56	46	31	24	5F	PB6 or	IO/Z	I	Multiplexed pin whose function is selected by the
					FD[6]		(PB6)	following bits: IFCONFIG[1..0].
								PB6 is a bidirectional IO port pin.
								FD[6] is the bidirectional FIFO/GPIF data bus.
57	47	32	25	6H	PB7 or	IO/Z	I	Multiplexed pin whose function is selected by the
					FD[7]		(PB7)	following bits: IFCONFIG[1..0].
								PB7 is a bidirectional IO port pin.
								FD[7] is the bidirectional FIFO/GPIF data bus.
PORT	C
72	57				PC0 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR0		(PC0)	PORTCCFG.0
								PC0 is a bidirectional IO port pin.
								GPIFADR0 is a GPIF address output pin.
73	58				PC1 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR1		(PC1)	PORTCCFG.1
								PC1 is a bidirectional IO port pin.
								GPIFADR1 is a GPIF address output pin.
74	59				PC2 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR2		(PC2)	PORTCCFG.2
								PC2 is a bidirectional IO port pin.
								GPIFADR2 is a GPIF address output pin.
75	60				PC3 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR3		(PC3)	PORTCCFG.3
								PC3 is a bidirectional IO port pin.
								GPIFADR3 is a GPIF address output pin.
76	61				PC4 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR4		(PC4)	PORTCCFG.4
								PC4 is a bidirectional IO port pin.
								GPIFADR4 is a GPIF address output pin.
77	62				PC5 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR5		(PC5)	PORTCCFG.5
								PC5 is a bidirectional IO port pin.
								GPIFADR5 is a GPIF address output pin.
78	63				PC6 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR6		(PC6)	PORTCCFG.6
								PC6 is a bidirectional IO port pin.
								GPIFADR6 is a GPIF address output pin.
79	64				PC7 or	IO/Z	I	Multiplexed pin whose function is selected by
					GPIFADR7		(PC7)	PORTCCFG.7
								PC7 is a bidirectional IO port pin.
								GPIFADR7 is a GPIF address output pin.
PORT	D
102	80	52	45	8A	PD0 or	IO/Z	I	Multiplexed pin whose function is selected by the
					FD[8]		(PD0)	IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
								FD[8] is the bidirectional FIFO/GPIF data bus.
103	81	53	46	7A	PD1 or	IO/Z	I	Multiplexed pin whose function is selected by the
					FD[9]		(PD1)	IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.
								FD[9] is the bidirectional FIFO/GPIF data bus.
Document #: 38-08032 Rev. *L								Page 24 of 62

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