Motorola 24-Bit Digital Signal Processor, DSP56000 DSP56K Block Diagram Offset Register Files Nn

AGU ARCHITECTURE

								EXPANSION
								AREA
		PERIPHERAL		PROGRAM		X MEMORY	Y MEMORY
				RAM/ROM		RAM/ROM	RAM/ROM
		MODULES
PERIPHERAL PINS				EXPANSION		EXPANSION	EXPANSION
			ADDRESS		YAB			EXTERNAL	ADDRESS
					XAB
		GENERATION						ADDRESS
					PAB
	24-Bit 56K		UNIT					BUS
	Module							SWITCH
										A
								BUS	CONTROL	PORT
								CONTROL
					YDB
	INTERNAL				XDB			EXTERNAL	DATA
	DATA							DATA BUS
	BUS				PDB			SWITCH
	SWITCH
					GDB
	PLL					DATA ALU
		PROGRAM	PROGRAM	PROGRAM
						24X24+56→56-BIT MAC		OnCE™
	CLOCK	INTERRUPT	DECODE	ADDRESS
		CONTROLLER	CONTROLLER	GENERATOR	TWO 56-BIT ACCUMULATORS
	GENERATOR		Program Control Unit
			MODC/NMI

16 BITS

MODB/IRQB		24 BITS
MODA/IRQA
	RESET

Figure 4-1 DSP56K Block Diagram

4.2.2 Offset Register Files (Nn)

Each of two offset register files shown in Figure 4-2consists of four 16-bit registers. The two files contain offset registers N0 - N3 and N4 - N7, which contain either data or offset values used to update address pointers. Each offset register can be read or written by the

4 - 4 ADDRESS GENERATION UNIT MOTOROLA