EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

CAUTION

On all level-sensitive interrupts, the interrupt must be externally released be- fore interrupts are internally re-enabled. Otherwise, the processor will be in- terrupted repeatedly until the release of the level-sensitive interrupt occurs.

The edge sensitive NMI is a priority 3 interrupt and cannot be masked. Only RESET and illegal instruction have higher priority than NMI.

7.3.3.2 Software Interrupt Sources

There are two software interrupt sources — software interrupt (SWI) and illegal instruc- tion interrupt (III).

SWI is a nonmaskable interrupt (IPL 3), which is serviced immediately following the SWI instruction execution, usually using a long interrupt service routine. The difference between an SWI and a JSR instruction is that the SWI sets the interrupt mask to prevent interrupts below IPL 3 from being serviced. The SWI’s ability to mask out lower level interrupts makes it very useful for setting breakpoints in monitor programs. The JSR instruction does not affect the interrupt mask.

The III is also a nonmaskable interrupt (IPL 3). It is serviced immediately following the execution or the attempted execution of an illegal instruction (any undefined operation code). IIIs are fatal errors. Only a long interrupt routine should be used for the III routine. RTI or RTS should not be used at the end of the interrupt routine because, during the III service, the JSR located in the III vector will normally stack the address of the illegal instruction (see Figure 7-4). Returning from the interrupt routine would cause the proces- sor to attempt to execute the illegal interrupt again and cause an infinite loop which can only be broken by cycling power. This long interrupt (see Figure 7-4)can be used as a diagnostic tool to allow the programmer to examine the stack (MOVE SSH, dest) and locate the illegal instruction, or the application program can be restarted with the hope that the failure was a soft error. The illegal instruction is useful for triggering the illegal interrupt service routine to see if the III routine can recover from illegal instructions.

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PROCESSING STATES

MOTOROLA

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Motorola 24-Bit Digital Signal Processor, DSP56000 manual Software Interrupt Sources