EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)
MOTOROLA PROCESSING STATES 7 - 23
NOP
MAIN
PROGRAM
FETCHES
n1
TRACE BIT
SET IN SR
TRACE INSTRUCTION n1
n2
NOP
NOP
JSR
NOT USED
RTI
DEBUGGER
PROGRAM
NEXT TRACE
OPERATION
THREE NOP
INSTRUCTIONS INSERTED
BY TRACE MODE
FAST INTERRUPT
CAUSED BY TRACE
INTERRUPT
SET TRACE BIT IN SSL
(a) Instruction Fetches from Memory
INTERRUPT CONTROL CYCLE 1 i i
INTERRUPT CONTROL CYCLE 2 i i
FETCH n1 NOP NOP NOP JSR — TRACE PROGRAM RTI — n2 NOP NOP NOP
DECODE n1 NOP NOP NOP JSR NOP TRACE PROGRAM RTI NOP n2 NOP NOP NOP
EXECUTE n1 NOP NOP NOP JSR NOP TRACE PROGRAM RTI NOP n2 NOP NOP NOP
INSTRUCTION CYCLE COUNT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
i = INTERRUPT
ii = INTERRUPT INSTRUCTION WORD
II = ILLEGAL INSTRUCTION
n = NORMAL INSTRUCTION WORD
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
INTERRUPT SYNCHRONIZED AND
RECOGNIZED AS PENDING
Figure 7-7 Trace Exception
(b) Program Controller Pipeline