Motorola 24-Bit Digital Signal Processor, DSP56000 manual Introduction

INTRODUCTION

B.1 INTRODUCTION

Table B-1provides benchmark numbers for 18 common DSP programs implemented on the 27-MHz DSP56001.

The four code examples shown in Figures B-1 to B-4 represent the benchmark programs shown in Table B-1.

B.2 BENCHMARK PROGRAMS

Figure B-1 is the code for the 20-tap FIR filter shown in Table B-1.Figure B-2 is the code for an FFT using a triple nested DO LOOP. Although this code is easier to understand and very compact, it is not as fast as the code used for the benchmarks shown in Table B-1,which are highly optimized using the symmetry of the FFT and the parallelism of the DSP. Figure B-3 is the code for the 8-pole cascaded canonic biquad IIR filter, which uses four coefficients (see Table B-1). Figure B-4 is the code for a 2N delayed least mean square (LMS) FIR adaptive filter, which is useful for echo cancelation and other adaptive filtering applications.The code example shown in Figure B-5 represents the Real FFT code for the DSP56002, based on the Glenn Bergland algorithm.

The code for these and other programs is free and available through the Dr. BuB elec- tronic bulletin board.

MOTOROLA BENCHMARK PROGRAMS B - 3