PLL OPERATION CONSIDERATIONS
9 - 14 PLL CLOCK OSCILLATOR MOTOROLA
While the PLL is regaining lock, the CKOUT clock output remains at the same logic level
it held when the PLL lost lock, which is when the clocks were frozen in the DSP.
When the chip enters the WAIT processing state, the core phases are disabled but CK-
OUT continues to operate. When PLL is disabled, CKOUT will be fed from EXTAL.
If DF>1 and CKOS≠CSRC, then the programmer must change either CKOS or CSRC be-
fore taking any action that causes the PLL to lose and subsequently regain lock, such as
changing the multiplication factor, enabling PLL operation, or recovering from the STOP
state with PSTP=0.
Any change of the CKOS or CSRC bits must be done while DF=1.
9.4.9 Synchronization Among EXTAL, CKOUT, and the Internal Clock
Low clock skew between EXTAL and CKOUT is guaranteed only if MF≤4. The synchro-
nization between CKOUT and the internal chip activity and Port A timing is guaranteed in
all cases where CKOS=CSRC and the bits have never differed from one another.