Motorola DSP56000, 24-Bit Digital Signal Processor manual Bit Test and Set, Condition Codes

INSTRUCTION DESCRIPTIONS

BSET

Bit Test and Set

Explanation of Example: Prior to execution, the 24-bit X location X:$FFE5 (I/O port C data register) contains the value $000000. The execution of the BSET #$0,X:<<$FFE5 instruction tests the state of the 0th bit in X:$FFE5, sets the carry bit C accordingly, and then sets the 0th bit in X:$FFE5.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3	2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U	N	Z		V	C
				MR									CCR

CCR Condition Codes:

For destination operand SR:

C — Set if bit 0 is specified. Not affected otherwise.

V — Set if bit 1 is specified. Not affected otherwise.

Z — Set if bit 2 is specified. Not affected otherwise.

N — Set if bit 3 is specified. Not affected otherwise.

U — Set if bit 4 is specified. Not affected otherwise.

E — Set if bit 5 is specified. Not affected otherwise.

L — Set if bit 6 is specified. Not affected otherwise.

S — Set if bit 7 is specified. Not affected otherwise.

For destination operand A or B:

S —Computed according to the definition. See Notes on page A-63.L — Set if data limiting has occurred. See Notes on page A-63.

E — Not affected

U — Not affected

N — Not affected

Z — Not affected

V — Not affected

C — Set if bit tested is set. Cleared otherwise.

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