NORMAL PROCESSING STATE
MOTOROLA
PROCESSING STATES 7 - 7
Note 1:
INST 3 may be executed at that point only if the preceding instruction (INST 2)
was a single-word instruction.
Note 2:
II=Interrupt instruction from maskable interrupt.
The following program flow will not occur because the new interrupt mask level becomes
effective after a pipeline latency of four instruction cycles:
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ORI #03,MR ;Disable interrupts.
INST 1
INST 2
INST 3
INST 4
II ;Interrupts disabled.
II+1 ;Interrupts disabled.
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1. Program flow without interrupts after interrupts are re-enabled:
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ANDI #00,MR ;Enable interrupts
INST 1
INST 2
INST 3
INST 4
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2. Program flow with interrupts after interrupts are re-enabled:
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ANDI #00,MR ;Enable interrupts
INST 1 ;Uninterruptable
INST 2 ;Uninterruptable
INST 3 ;II fetched
INST 4 ;II+1 fetched
II
II+1
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