Motorola 24-Bit Digital Signal Processor, DSP56000 manual Interrupt Priority Structure

EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING)

fetches only two words and then automatically resumes execution of the main program; whereas, the long interrupt must be told to return to the main program by executing an RTI instruction. The fast routine consists of two automatically inserted interrupt instruc- tion words. These words can contain any unrestricted, single two-word instruction or any two one-word instructions (see Section A.9 in APPENDIX A - INSTRUCTION SET DETAILS for a list of restrictions). Fast interrupt routines are never interruptible.

CAUTION

Status is not preserved during a fast interrupt routine; therefore, instructions that modify status should not be used at the interrupt starting address and interrupt starting address +1.

If one of the instructions in the fast routine is a JSR, then a long interrupt routine is formed. The following actions occur during execution of the JSR instruction when it occurs in the interrupt starting address or in the interrupt starting address +1:

1.The PC (containing the return address) and the SR are stacked.

2.The loop flag is reset.

3.The scaling mode bits are reset.

4.The IPL is raised to disallow further interrupts at the same or lower levels (except that hardware RESET, NMI, stack error, trace, and SWI can always interrupt).

5.The trace bit in the SR is cleared (in the DSP56000/56001 only).

The long interrupt routine should be terminated by an RTI. Long interrupt routines are interruptible by higher priority interrupts. Figure 7-1shows examples of fast and long interrupts.

7.3.2 Interrupt Priority Structure

Interrupts are organized in a flexible priority structure. Each interrupt has an associated interrupt priority level (IPL) that can range from zero to three. Levels 0 (lowest level), 1, and 2 are maskable. Level 3 is the highest IPL and is not maskable. The only IPL 3 inter- rupts are RESET, illegal instruction interrupt (III), nonmaskable interrupt (NMI), stack error, trace, and software interrupt (SWI). The interrupt mask bits (I1, I0) in the SR reflect the current priority level and indicate the IPL needed for an interrupt source to interrupt the processor (see Table 7-2). Interrupts are inhibited for all priority levels below the cur- rent processor priority level. However, level 3 interrupts are not maskable and therefore can always interrupt the processor. DSP56K Family central processor interrupt sources

7 - 12 PROCESSING STATES MOTOROLA