Motorola DSP56000, 24-Bit Digital Signal Processor manual Condition Codes, Lsl D

INSTRUCTION DESCRIPTIONS

LSL Logical Shift Left

Condition Codes:

LSL

15	14	13	12	11		10	9		8	7	6	5	4	3	2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U	N	Z		V	C
				MR									CCR

S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move

N — Set if bit 47 of A or B result is set

Z — Set if bits 47–24 of A or B result are zero V — Always cleared

C — Set if bit 47 of A or B was set prior to instruction execution

Instruction Format:

LSL D

Opcode:

23		8	7	4	3	0
	DATA BUS MOVE FIELD		0 0 1	1	d	0 1 1
	OPTIONAL EFFECTIVE ADDRESS EXTENSION

Instruction Fields:

Dd A 0 B 1

Timing: 2+mv oscillator clock cycles

Memory: 1+mv program words

MOTOROLA INSTRUCTION SET DETAILS A - 145