Motorola 24-Bit Digital Signal Processor manual Address Register Update Operation Assembler Syntax

INSTRUCTION DESCRIPTIONS

U		Address Register Update
Operation:		Assembler Syntax:
(	); ea➞Rn	(	) ea

U

where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Update the specified address register according to the specified effective addressing mode. All update addressing modes may be used.

Example:

:

RND B (R3)+N3 ;round value in B into B1, R3+N3➞R3

:

R3

Before Execution

$0007

R3

After Execution

$000B

N3

$0004

N3

$0004

Explanation of Example: Prior to execution, the 16-bit address register R3 contains the value $0007, and the 16-bit address offset register N3 contains the value $0004. The execution of the parallel move portion of the instruction, (R3)+N3, updates the R3 address register according to the specified effective addressing mode by adding the value in the R3 register to the value in the N3 register and storing the 16-bit result back in the R3 address register.

Condition Codes:

15	14	13	12	11		10	9		8	7	6	5	4	3	2	1		0
LF	DM	T	**		S1	S0		I1	I0	S	L	E	U	N	Z		V	C
				MR									CCR

The condition codes are not affected by this type of parallel move.

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