Motorola 24-Bit Digital Signal Processor, DSP56000 manual Move

INSTRUCTION DESCRIPTIONS

MOVE

Move Data

MOVE

Parallel Move Descriptions: Thirty of the sixty-two instructions allow an optional paral- lel data bus movement over the X and/or Y data bus. This allows a data ALU operation to be executed in parallel with up to two data bus moves during the instruction cycle. Ten types of parallel moves are permitted, including register to register moves, register to memory moves, and memory to register moves. However, not all addressing modes are allowed for each type of memory reference. Addressing mode restrictions which apply to specific types of moves are noted in the individual move operation descriptions. The fol- lowing section contains detailed descriptions about each type of parallel move operation.

When a 56-bit accumulator (A or B) is specified as a source operand S, the accumulator value is optionally shifted according to the scaling mode bits S0 and S1 in the system status register (SR). If the data out of the shifter indicates that the accumulator extension register is in use and the data is to be moved into a 24- or 48-bit destination, the value stored in the destination D is limited to a maximum positive or negative saturation con- stant to minimize truncation error. Limiting does not occur if an individual 24-bit accumu- lator register (A1, A0, B1, or B0) is specified as a source operand instead of the full 56-bit accumulator (A or B). This limiting feature allows block floating-point operations to be performed with error detection since the L bit in the condition code register is latched.

Note: Whenever an instruction uses an accumulator as both a destination operand for a data ALU operation and as a source for a parallel move operation, the parallel move operation occurs first and will use the data that exists in the accumulator before the execution of the data ALU operation has occurred.

A - 160 INSTRUCTION SET DETAILS MOTOROLA