Motorola 24-Bit Digital Signal Processor manual Long Memory Data Move Operation Assembler Syntax

INSTRUCTION DESCRIPTIONS

	L:	Long Memory Data Move		L:
Operation:			Assembler Syntax:
(		); X:ea ➞ D1; Y:ea ➞ D2	(	) L:ea,D
(		); X:aa ➞ D1; Y:aa ➞ D2	(	) L:aa,D
(		); S1 ➞ X:ea; S2 ➞ Y:ea	(	) S,L:ea
(		); S1 ➞ X:aa; S2 ➞ Y:aa	(	) S,L:aa

where ( . . . . . ) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Move one 48-bit long-word operand from/to X and Y memory. Two data ALU registers are concatenated to form the 48-bit long-word operand. This allows effi- cient moving of both double-precision (high:low) and complex (real:imaginary) data from/ to one effective address in L (X:Y) memory. The same effective address is used for both the X and Y memory spaces; thus, only one effective address is required. Note that the A, B, A10, and B10 operands reference a single 48-bit signed (double-precision) quantity while the X, Y, AB, and BA operands reference two separate (i.e., real and imaginary) 24-bit signed quantities. All memory alterable addressing modes may be used. Absolute short addressing may also be used.

If the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumulator, that same accumulator or portion of that accumulator may not be specified as a destination D in the parallel data bus move operation. Thus, if the opcode-operand portion of the instruction specifies the 56-bit A accumulator as its desti- nation, the parallel data bus move portion of the instruction may not specify A, A10, AB, or BA as destination D. Similarly, if the opcode-operand portion of the instruction speci- fies the 56-bit B accumulator as its destination, the parallel data bus move portion of the instruction may not specify B, B10, AB, or BA as its destination D. That is, duplicate des- tinations are NOT allowed within the same instruction.

If the opcode-operand portion of the instruction specifies a given source or destination register, that same register or portion of that register may be used as a source S in the parallel data bus move operation. This allows data to be moved in the same instruction in which it is being used as a source operand by a data ALU operation. That is, duplicate sources are allowed within the same instruction.

Note: The operands A10, B10, X, Y, AB, and BA may be used only for a 48-bit long memory move as previously described. These operands may not be used in any other type of instruction or parallel move.

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