Motorola 24-Bit Digital Signal Processor, DSP56000 manual Shift Right and Subtract Accumulators

INSTRUCTION DESCRIPTIONS

	SUBR	Shift Right and Subtract Accumulators		SUBR
Operation:			Assembler Syntax:
	D/2–S ➞ D (parallel move)		SUBR S,D (parallel move)

Description: Subtract the source operand S from one-half the destination operand D and store the result in the destination accumulator. The destination operand D is arith- metically shifted one bit to the right while the MS bit of D is held constant prior to the sub- traction operation. In contrast to the SUBL instruction, the carry bit is always set correctly, and the overflow bit can only be set by the subtraction operation, and not by an overflow due to the initial shifting operation. This instruction is useful for efficient divide and decimation in time (DIT) FFT algorithms.

Example:

:

SUBR B,A N5,Y:–(R5)

:

		Before Execution
A
	$80:000000:2468AC

;A/2–B ➞ A, update R5, save N5

	After Execution
A
	$C0:000000:000000

B$00:000000:123456

B

$00:000000:123456

Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:000000:123456. The SUBR B,A instruction subtracts the value in the B accumulator from one-half the value in the A accumulator and stores the 56-bit result in the A accu- mulator.

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