OVERVIEW AND DATA ALU ARCHITECTURE
MOTOROLA
DATA ARITHMETIC LOGIC UNIT 3 - 7
3.2.3 Data ALU A and B Accumulators
The Data ALU features two general-purpose, 56-bit accumulators, A and B. Each con-
sists of three concatenated registers (A2:A1:A0 and B2:B1:B0, respectively). The 8-bit
sign extension (EXT) is stored in A2 or B2 and is used when more than 48-bit accuracy is
needed; the 24-bit most significant product (MSP) is stored in A1 or B1; the 24-bit least
Figure 3-3 MAC Unit
24 BITS
48 BITS
56 BITS
X0,X1,
Y0, OR Y1
X0,X1,
Y0, OR Y1
X0,X1,
Y0, OR Y1
24-BITx24-BIT
FRACTIONAL
MULTIPLIER
56 - BIT
ARITHMETIC AND
LOGIC UNIT
R24
S
H
I
F
T
E
R
CONVERGENT - ROUNDING
FORCING FUNCTION SCALING
MODE BITS
CONDITION
CODE GENERATOR
ACCUMULATOR A ACCUMULATOR B
+–