Motorola DSP56000, 24-Bit Digital Signal Processor manual MAC Unit Data ALU a and B Accumulators

OVERVIEW AND DATA ALU ARCHITECTURE

24 BITS	X0,X1,	X0,X1,	X0,X1,
48 BITS	Y0, OR Y1	Y0, OR Y1	Y0, OR Y1
56 BITS

	24-BITx24-BIT
	FRACTIONAL
	MULTIPLIER
		56 - BIT
		ARITHMETIC AND
S		LOGIC UNIT
H
I	+	R24
F
T	–
E
R
	CONVERGENT - ROUNDING	SCALING
	FORCING FUNCTION	MODE BITS
		CONDITION
	CODE GENERATOR
ACCUMULATOR A		ACCUMULATOR B

Figure 3-3 MAC Unit

3.2.3 Data ALU A and B Accumulators

The Data ALU features two general-purpose, 56-bit accumulators, A and B. Each con- sists of three concatenated registers (A2:A1:A0 and B2:B1:B0, respectively). The 8-bit sign extension (EXT) is stored in A2 or B2 and is used when more than 48-bit accuracy is needed; the 24-bit most significant product (MSP) is stored in A1 or B1; the 24-bit least

MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 7